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| 型号： | A8582KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 18/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 16TSSOP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.7 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 250kHz ~ 2.45MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-TSSOP-EP |
| 其它名称： | 620-1395-6 |
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A8582
Wide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
To calculate the second term in equation 6, Δ V ESL , we must
determine the slope of the output inductor current, di/dt, which is
(V IN – V OUT ) / L O :
? V CO =
? I L T S
8 C OUT
=
? I L
8 f SW C OUT
(9)
= ESL CO × IN
? V ESL = L O
di
dt
V – V OUT
L O
(8)
Combining equations 7, 8, and 9 results in an expression for the
total output voltage ripple:
To calculate the third term in equation 6, we must understand
? V OUT = ? I L × ESR CO +
8 f SW C OUT
L O
that, over a single PWM cycle, the amount of charge into the
output capacitors must equal the amount of charge out of the
capacitors, or the capacitor output voltages would drift. What this
means is the output inductor current ( Δ I L ) flows in and out of the
output capacitor and is centered at 0 A, as shown in figure 12.
V IN – V OUT ? I L
× ESL CO +
The type of output capacitors will determine which terms of
equation 10 are dominant.
(10)
i × dt
? V CO ≥
? V OUT =
? I L
8 f SW C OUT
A 1 = 1 ×
? I L DT S ? I L DT S
× =
For any capacitor, the voltage is:
1
C OUT
In this case, the integral term can be graphically calculated by
examining the 2 areas, A1 and A2, shown in figure 12:
2 2 2 8
For ceramic output capacitors the ESR and ESL are extremely
low, so the output voltage ripple will be dominated by the third
term of equation 10:
(10a)
To reduce the voltage ripple of a design using ceramic output
capacitors, simply: increase the total capacitance, reduce the
inductor current ripple (that is, increase the inductor value), or
A 2 = 1 ×
? I L T S
= –
2
? I L
2
×
(1 – D ) T S
2
8
? I L DT S
8
increase the switching frequency.
For electrolytic output capacitors the value of capacitance will be
? I L T S
i × dt = A 1 + A 2 =
? V OUT = ? I L × ESR CO + IN
L O
8
Substituting this into the equation for Δ V CO results in:
relatively high, so the third term in equation 10 will be minimized
and the output voltage ripple will be determined primarily by the
first two terms of equation 10:
V – V OUT
× ESL CO (10b)
To reduce the voltage ripple of a design using electrolytic output
I CO (A)
T S
capacitors, simply: decrease the equivalent ESR and ESL by
using a high(er) quality capacitor, and/or add more capacitors in
? I L / 2
DT S
(1 – D)T S
parallel, or reduce the inductor current ripple (that is, increase
the inductor value). The ESR of some electrolytic capacitors
can be quite high, so Allegro recommends choosing a quality
capacitor that clearly documents the ESR or the total impedance
0
A1
A2
in the datasheet. Also, the ESR of electrolytic capacitors usu-
ally increases significantly at cold ambient, which increases the
– ? I L / 2
DT S /2
[(1 – D)T S ]/2
Time
output voltage ripple and, in many cases, reduces the stability of
the system.
To reduce the output voltage ripple and save PCB area, a design
could combine both ceramic and electrolytic capacitors in paral-
lel. If this is done, the ceramic capacitors should be placed and
Figure 12. Output capacitor current waveform
grounded as close as possible to the load to be most effective. AC
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
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| A8583KLPTR-T | 功能描述:IC REG BUCK ADJ 3.5A 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:50 系列:- 类型:升压（升压） 输出类型:可调式 输出数:1 输出电压:5 V ~ 25 V 输入电压:2.3 V ~ 5.5 V PWM 型:电流模式 频率 - 开关:600kHz，1.2MHz 电流 - 输出:1A 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装:管件 供应商设备封装:8-MSOP |
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