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参数资料
| 型号： | A8582KLPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 21/32页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 2A 16TSSOP |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 4.7 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 250kHz ~ 2.45MHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 16-TSSOP-EP |
| 其它名称： | 620-1395-6 |
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C SS ≥
20 ( μ A) × V OUT × C OUT
0.8 (V) × I CO
A8582
charge the output capacitors (I CO = C O × dV OUT /dt SS ) is higher
than the pulse-by-pulse current threshold, as shown in figure 14.
This phenomena is more pronounced when using high value
electrolytic type output capacitors.
To avoid prematurely triggering hiccup mode the soft start
capacitor, CSS, should be calculated using the following formula:
(16)
Where V OUT is the output voltage, C OUT is the output capaci-
tance, I CO is the amount of current allowed to charge the output
capacitance during soft start (Allegro recommends 0.125 A < I CO
< 0.375 A). Higher values of I CO result in faster soft start times.
However, lower values of I CO insure that Hiccup mode is not
falsely triggered as components vary.
Components can easily change due to initial tolerances, aging, or
temperature (output capacitance, soft start capacitance, soft start
charging currents, and so forth). Allegro recommends starting the
design with an I CO of 0.125 A and increasing it only if the soft
start time is too slow. If a non-standard capacitor value for C SS is
calculated, the next larger value should be used.
The output voltage ramp time, t SS , can be calculated by using
either of the following formulas:
Wide Input Voltage, 2.4 MHz , 2.0 A
Asynchronous Buck Regulator
When the A8582 is in Hiccup mode, the CSS capacitor is used as
a timing capacitor and sets the hiccup period. The SS pin charges
the CSS capacitor with I SSSU (nominally 20 μ A) during a startup
attempt and discharges the CSS capacitor with I SSHIC (nominally
10 μ A) between startup attempts. Because the ratio of the SS pin
currents is 2:1, the time between hiccups will be at least twice
as long as the startup time. Therefore, the effective duty-cycle of
the A8582 will be very low when the output is shorted to ground.
With such a low duty cycle, the junction temperature of the
A8582 will be maintained at an extremely low value, compared
to other short circuit protection techniques.
Compensation Components (RZ, CZ, CP)
To compensate the system it is important to understand where the
buck power stage, load resistance, and output capacitance form
their poles and zeros in frequency. Also, it is important to under-
stand that the compensated Error amplifier introduces a zero and
two more poles, and also where these should be placed to maxi-
mize system stability, provide a high bandwidth, and optimize the
transient response.
First, we will take a look at the power stage of the A8582, the
output capacitors, and the load resistance. This circuitry is com-
monly referred as the “control to output” transfer function. The
t SS = V OUT ×
t SS = 0.8 (V) ×
or
C OUT
I CO
C SS
20 ( μ A)
(17a)
(17b)
low frequency gain of this section depends on the COMP to
SW current gain (g mPOWER ), and the value of the load resistor
(R LOAD ). The DC gain of the control-to-output is:
G CO = g mPOWER × R LOAD (18)
The control-to-output transfer function has a pole (f P1 ) formed by
the output capacitance (C OUT ) and load resistance (R LOAD ) at:
I OUT (A)
f P1 =
1
2 × R LOAD × C OUT
(19)
2 × ESR × C OUT
I LIM
I LOAD
}
I CO
The control-to-output transfer function also has a zero (f Z1 )
formed by the output capacitance (C OUT ) and its associated ESR:
1
f Z1 = (20)
For a design with very low-ESR type output capacitors (for exam-
t SS
Time
Figure 14. Output capacitor current (I CO ) during startup
ple, ceramic or OSCON output capacitors), the ESR zero (f Z1 )
is usually at a high frequency, so it can be ignored. On the other
hand, if the ESR zero falls below or near the 0 dB crossover fre-
quency of the system (such as with electrolytic output capacitors),
then it should be cancelled by the pole formed by the CP capacitor
and the RZ resistor (discussed and identified later as f P3 ).
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21
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| A8583KLPTR-T | 功能描述:IC REG BUCK ADJ 3.5A 16TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:50 系列:- 类型:升压（升压） 输出类型:可调式 输出数:1 输出电压:5 V ~ 25 V 输入电压:2.3 V ~ 5.5 V PWM 型:电流模式 频率 - 开关:600kHz，1.2MHz 电流 - 输出:1A 同步整流器:无 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装:管件 供应商设备封装:8-MSOP |
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