参数资料
| 型号： | XRT83SL34IV |
| 厂商： | Exar Corporation |
| 文件页数： | 15/80页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 QUAD 128TQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 4/4 |
| 规程： | T1，E1，J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
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XRT83SL34
QUAD T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
19
In Host mode the programming is achieved through the corresponding interface control bits, the state of the
CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit.
RECEIVER
In Hardware mode all receive channels are turned on upon power-up and there is no provision supplied to
power them off. In Host mode, each receiver channel can be individually powered on or off with its respective
channel RXON_n bit. See “Microprocessor Register #0, Bit Description” on page 45.
RECEIVER INPUT
At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1
transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum
equalizer gain is up to 36 dB for both T1 and E1 modes. The equalized signal is subsequently applied to a
peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1
and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital
representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data
subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before
being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital
phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of
input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards.
TABLE 1: MASTER CLOCK GENERATOR
MCLKE1
K
HZ
MCLKT1
K
HZ
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
MASTER CLOCK
K
HZ
2048
0
2048
0
1
1544
2048
1544
0
2048
1544
0
1
1544
0
1
0
2048
1544
0
1
1544
8
x
01
00
2048
8
x
01
1544
16
x
0
1
0
2048
16
x
0
1
1544
56
x
1
0
2048
56
x
1
0
1
1544
64
x
1
0
1
0
2048
64
x
1
0
1
1544
128
x
11
00
2048
128
x
11
01
1544
256
x
11
10
2048
256
x
11
1544
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT83SL34IV-F | 功能描述:时钟合成器/抖动清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| XRT83SL38 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR |
| XRT83SL38_07 | 制造商:EXAR 制造商全称:EXAR 功能描述:OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER |
| XRT83SL38ES | 功能描述:外围驱动器与原件 - PCI 8 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT83SL38ES-BG | 功能描述:界面开发工具 Eval System for XRT83SL38 Series RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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