参数资料
型号: A1425A-STDCQ132B
元件分类: FPGA
英文描述: FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132
封装: CERAMIC, QFP-132
文件页数: 6/54页
文件大小: 343K
代理商: A1425A-STDCQ132B
RadTolerant FPGAs
1- 10
v3.1
To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic
must be known. EQ 1-5 shows a piece-wise linear summation over all components. Since the RT1280A and A1280A
have two routed array clocks, the dedicated_Clk and IO_Clk terms do not apply. For all other devices all terms apply.
Power = VCC
2 * [(m * C
EQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1
*fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk]
EQ 1-5
where:
m
=
Number of logic modules switching at fm
n
=
Number of input buffers switching at fn
p
=
Number of output buffers switching at fp
q1
=
Number of clock loads on the first routed array
clock
q2
=
Number of clock loads on the second routed array
clock (not applicable for RT1020 or A1020B)
r1
=
Fixed capacitance due to first routed array clock
r2
=
Fixed capacitance due to second routed array clock
(not applicable for RT1020 or A1020B)
s1
=
Fixed number of clock loads on the dedicated array
clock
(not
applicable
for
RT1020,
A1020B,
RT1280A, or A1280A)
s2
=
Fixed number of clock loads on the dedicated
I/O clock (not applicable for RT1020, A1020B,
RT1280A, or A1280A)
CEQM =
Equivalent capacitance of logic modules in pF
CEQI
=
Equivalent capacitance of input buffers in pF
CEQO
=
Equivalent capacitance of output buffers in pF
CEQCR =
Equivalent capacitance of routed array clock in pF
CEQCD =
Equivalent capacitance of dedicated array clock
in pF
CEQCI =
Equivalent capacitance of dedicated I/O clock in pF
CL
=
Output lead capacitance in pF
fm
=
Average logic module switching rate in MHz
fn
=
Average input buffer switching rate in MHz
fp
=
Average output buffer switching rate in MHz
fq1
=
Average first routed array clock rate in MHz
fq2
=
Average second routed array clock rate in MHz (not
applicable for RT1020 or A1020B)
fs1
=
Average dedicated array clock rate in MHz (not
applicable for RT1020, A1020B, RT1280A, or
A1280A)
fs2
=
Average dedicated I/O clock rate in MHz
(not applicable for RT1020, A1020B, RT1280A, or
A1280A)
Table 1-8 Fixed Capacitance Values for Actel FPGAs (pF)
Device Type
r1
routed_Clk1
r2
routed_Clk2
RT1020, A1020B
69
n/a
RT1280A, A1280A
168
RT1425A, A1425A
75
RT1460A, A1460A
165
RT14100A, A14100A
195
Table 1-9 Fixed Clock Loads (s1/s2 – ACT 3 Only)
Device Type
s1
Clock Loads
on Dedicated
Array Clock
s2
Clock Loads
on Dedicated
I/O Clock
RT1425A, A1425A
160
100
RT1460A, A1460A
432
168
RT14100A, A14100A
697
228
相关PDF资料
PDF描述
A1425A-STDCQ132C FPGA, 310 CLBS, 7500 GATES, CQFP132
A1425A-STDCQ132M FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132
A14100A-STDCQG256B FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256
A14100A-STDCQG256M FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256
A1460A-1PQ160M FPGA, 848 CLBS, 6000 GATES, 125 MHz, PQFP160
相关代理商/技术参数
参数描述
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