- 您现在的位置：买卖IC网 > PDF目录294782 > A1425A-STDCQ132B FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132 PDF资料下载
参数资料
| 型号： | A1425A-STDCQ132B |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132 |
| 封装： | CERAMIC, QFP-132 |
| 文件页数： | 53/54页 |
| 文件大小： | 343K |
| 代理商： | A1425A-STDCQ132B |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页
RadTolerant FPGAs
1- 4
v3.1
The RT1020 Logic Module
The RT1020 logic module is an 8-input, 1-output logic
circuit chosen for the wide range of functions it
implements and for its efficient use of interconnect
routing resources (Figure 1-3).
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two,
three, or four inputs. Each function may have many
versions, with different combinations of active low
inputs. The logic module can also implement a variety of
D-latches, exclusivity functions, AND-ORs, and OR-ANDs.
No dedicated hardwired latches or flip-flops are required
in the array, since latches and flip-flops may be
constructed from logic modules wherever needed in the
application.
I/O Modules
I/O modules provide the interface between the device
pins and the logic array. A variety of user functions,
determined by a library macro selection, can be
implemented in the module (refer to the Macro Library
Guide for more information). I/O modules contain a
tristate buffer, and input and output latches that can be
configured for input, output, or bidirectional pins
The RadTolerant devices contain flexible I/O structures in
that each output pin has a dedicated output enable
control. The I/O module can be used to latch input and/or
output data, providing a fast setup time. In addition, the
Actel Designer software tools can build a D-flip-flop,
using a C-module, to register input and/or output
signals.
The Actel Designer software development tools provide
a design library of I/O macros. The I/O macro library
provides macro functions that can implement all I/O
configurations supported by the RadTolerant FPGAs.
Routing Structure
The RadTolerant device architecture uses vertical and
horizontal routing tracks to interconnect the various
logic and I/O modules. These routing tracks are metal
interconnects that may either be of continuous length or
broken into segments. Varying segment lengths allow
over 90% of the circuit interconnects to be made with
only two antifuse connections. Segments can be joined
together at the ends, using antifuses to increase their
length
up
to
the
full
length
of
the
track.
All
interconnects can be accomplished with a maximum of
four antifuses.
Horizontal Routing
Horizontal channels are located between the rows of
modules, and are composed of several routing tracks.
The horizontal routing tracks within the channel are
divided into one or more segments. The minimum
horizontal segment length is the width of a module-pair,
and the maximum horizontal segment length is the full
length of the channel. Any segment that spans more
than one-third the row length is considered a long
horizontal segment. A typical channel is shown in
Non-dedicated
horizontal
routing tracks are used to route signal nets. Dedicated
routing tracks are used for the global clock networks,
and for power and ground tie-off tracks.
Vertical Routing
Another set of routing tracks runs vertically through the
module. There are three types of vertical tracks that can
be divided into one or more segments: input, output,
and long. Each segment in an input track is dedicated to
the input of a particular module. Each segment in an
Figure 1-3 RT1020 Logic Module
Figure 1-4 I/O Module
G/CLK*
QD
EN
PAD
* Can be configured as a Latch or D-Flip-Flop
From Array
To Array
(Using C-Module)
G/CLK*
QD
相关PDF资料 |
PDF描述 |
|---|---|
| A1425A-STDCQ132C | FPGA, 310 CLBS, 7500 GATES, CQFP132 |
| A1425A-STDCQ132M | FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132 |
| A14100A-STDCQG256B | FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256 |
| A14100A-STDCQG256M | FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256 |
| A1460A-1PQ160M | FPGA, 848 CLBS, 6000 GATES, 125 MHz, PQFP160 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1425A-STDCQ132M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| A1425A-VQ100C | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| A1425A-VQ100I | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| A1425A-VQG100C | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| A1425A-VQG100I | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
发布紧急采购，3分钟左右您将得到回复。