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参数资料
| 型号： | A1425A-STDCQ132B |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132 |
| 封装： | CERAMIC, QFP-132 |
| 文件页数： | 29/54页 |
| 文件大小： | 343K |
| 代理商： | A1425A-STDCQ132B |
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RadTolerant FPGAs
v3.1
1-31
Pin Descriptions
CLK
Clock (Input)
RT1020 and A1020B only. TTL clock input for global clock
distribution networks. The clock input is buffered prior
to clocking the logic modules. This pin can also be used
as an I/O.
CLKA
Clock A (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
CLKB
Clock B (Input)
Not applicable for RT1020 and A1020B. TTL clock input
for global clock distribution networks. The clock input is
buffered prior to clocking the logic modules. This pin can
also be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-Wired) Array Clock
(Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for sequential modules. This
input is directly wired to each S-module, offering clock
speeds independent of the number of S-modules being
driven. This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bidirectional buffer.
Input
and
output
levels
are
compatible with standard TTL and CMOS specifications.
In the RT1020, A1020B, RT1280, and A1280A devices,
unused I/O pins are automatically driven LOW. In the
RT1425,
A1425A,
RT1460,
A1460A,
RT14100,
and
A14100A devices, unused I/O pins are automatically
tristated.
IOCLK
Dedicated (Hard-Wired) I/O Clock (Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL clock input for I/O modules. This input is
directly wired to each I/O module, offering clock speeds
independent of the number of I/O modules being driven.
This pin can also be used as an I/O.
IOPCL
Dedicated (Hard-Wired) I/O
Preset/Clear (Input)
Not applicable for RT1020, A1020B, RT1280A and
A1280A. TTL input for I/O preset or clear. This global
input is directly wired to the preset and clear inputs of all
I/O registers. This pin functions as an I/O when no I/O
preset or clear macros are used.
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the
pins function as I/Os. To provide debugging capability,
the MODE pin should be terminated to GND through a
10 k
resistor so that the MODE pin can be pulled HIGH
when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
B pin to allow real-time diagnostic output of any signal
path within the device. The Probe A pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRA is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any user-
defined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
A pin to allow real-time diagnostic output of any signal
path within the device. The Probe B pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRB is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
VCC
5.0 V Supply Voltage
HIGH supply voltage.
相关PDF资料 |
PDF描述 |
|---|---|
| A1425A-STDCQ132C | FPGA, 310 CLBS, 7500 GATES, CQFP132 |
| A1425A-STDCQ132M | FPGA, 310 CLBS, 7500 GATES, 100 MHz, CQFP132 |
| A14100A-STDCQG256B | FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256 |
| A14100A-STDCQG256M | FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256 |
| A1460A-1PQ160M | FPGA, 848 CLBS, 6000 GATES, 125 MHz, PQFP160 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1425A-STDCQ132M | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| A1425A-VQ100C | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| A1425A-VQ100I | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| A1425A-VQG100C | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
| A1425A-VQG100I | 功能描述:IC FPGA 2500 GATES 100-VQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ACT™ 3 产品变化通告:XC4000(E,L) Discontinuation 01/April/2002 标准包装:24 系列:XC4000E/X LAB/CLB数:100 逻辑元件/单元数:238 RAM 位总计:3200 输入/输出数:80 门数:3000 电源电压:4.5 V ~ 5.5 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:120-BCBGA 供应商设备封装:120-CPGA（34.55x34.55） |
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