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参数资料
| 型号： | 440EPX |
| 厂商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式处理器的PowerPC 440EPx |
| 文件页数： | 91/94页 |
| 文件大小： | 738K |
| 代理商： | 440EPX |
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440EPx – PPC440EPx Embedded Processor
Revision 1.26 – October 15, 2007
AMCC Proprietary
91
Preliminary Data Sheet
Initialization
The PPC440EPx provides the option for setting initial parameters based on default values or by reading them from
a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered
by strapping on external pins (see “Strapping” below).
Strapping
While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default
initial conditions prior to PPC440EPx start-up. The actual capture instant is the nearest reference clock edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. These pins are used for strap functions only during
reset. Following reset they are used for normal functions. The signal names assigned to the pins for normal
operation are shown in parentheses following the pin number.
Note: When UART0_DCD, UART0_DSR and UART0_CTS are used functionally, the pin straps should be isolated
from the UART transceiver during reset as the transceiver may overdrive the pin straps and cause the PPC440EPx
to read incorrect straps.
The following table lists the strapping pins along with their functions and strapping options:
Function
Option
Pin Strapping
C28
(UART0_DCD)
C29
(UART0_DSR)
A29
(UART0_CTS)
Serial device is disabled. Each of the six options (A–
F) is a combination of boot source, boot-source
width, and clock frequency specifications. Refer to
the IIC Bootstrap Controller chapter in the
PPC440EPx Embedded Processor User’s Manual
for details.
A
0
B
0
1
C
0
1
0
D
0
1
E
1
0
F
1
0
Serial device is enabled. The option being selected is
the IIC0 slave address that will respond with
strapping data.
G (0xA8)
1
0
1
H (0xA4)
1
Serial EEPROM
During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device
connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440EPx
sequentially reads 16B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1,
SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly.
The initialization settings and their default values are covered in detail in the PowerPC 440EPx User’s Manual.
Table 27. Strapping Pin Assignments
相关PDF资料 |
PDF描述 |
|---|---|
| 440EP | Power PC 440EP Embedded Processor |
| 440GP | Power PC 440GP Embedded Processor |
| 440GRX | PowerPC 440GRx Embedded Processor |
| 440GR | Power PC 440GR Embedded Processor |
| 440GX | Power PC 440GX Embedded Processor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 440ES001B1434-4 | 功能描述:环形MIL规格后盖 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440ES031M1633-3B | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRAIGHT BAND RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440ES031M2003-3B | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRAIGHT BAND RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440FA002NF1002-N | 功能描述:环形MIL规格后盖 RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440FA002NF1006-N | 功能描述:环形MIL规格后盖 RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
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