- 您现在的位置：买卖IC网 > PDF目录33779 > 440EPX (Applied Micro Circuits Corp.) PowerPC 440EPx Embedded Processor PDF资料下载
参数资料
| 型号： | 440EPX |
| 厂商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式处理器的PowerPC 440EPx |
| 文件页数： | 85/94页 |
| 文件大小： | 738K |
| 代理商： | 440EPX |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页当前第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页
440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
86
AMCC Proprietary
Revision 1.26 – October 15, 2007
insertion buffer.
When using unbuffered DIMMS, the loading on the address bus will be considerably greater than the clock (up to
18 loads for double-sided DIMMs). In this case, it is strongly suggested that a delay of 500ps in the clock path so
that the Address/Command setup time at the DIMMs can be met. This delay is sufficient to meet the setup time,
without having to change the programmable delay (internal to the PPC440EPx) between the DQS/DQ/DM and the
clock (assuming nominal settings as specified in the PPC440EPx Users Manual). While the clock is now 500ps
later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for TDQSS
(± 0.25 cycle, or 1.5ns at 166MHz). In the case where it is not possible to anticipate which kind of DIMMs may be
employed in a system, it is always safe to use this 500ps clock delay, since registered DIMMs (the least heavily
loaded) will have more than enough margin (almost 1/2 cycle) to accommodate the slight decrease in address hold
time.
Termination Model
Figure 10. DDR SDRAM Simulation Signal Termination Model
10pF
MemClkOut
120
Ω
50
Ω
30pF
Addr/Ctrl/Data/DQS/DM (DDR1)
VTT = SOVDD/2
PPC440EPx
Addr/Ctrl (DDR2)
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
DDR2 SDRAM On-Die Termination Impedance Setting
For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM
Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.
相关PDF资料 |
PDF描述 |
|---|---|
| 440EP | Power PC 440EP Embedded Processor |
| 440GP | Power PC 440GP Embedded Processor |
| 440GRX | PowerPC 440GRx Embedded Processor |
| 440GR | Power PC 440GR Embedded Processor |
| 440GX | Power PC 440GX Embedded Processor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 440ES001B1434-4 | 功能描述:环形MIL规格后盖 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440ES031M1633-3B | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRAIGHT BAND RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440ES031M2003-3B | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRAIGHT BAND RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440FA002NF1002-N | 功能描述:环形MIL规格后盖 RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440FA002NF1006-N | 功能描述:环形MIL规格后盖 RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
发布紧急采购，3分钟左右您将得到回复。