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参数资料
| 型号： | 440EPX |
| 厂商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 440EPx Embedded Processor |
| 中文描述： | 嵌入式处理器的PowerPC 440EPx |
| 文件页数： | 4/94页 |
| 文件大小： | 738K |
| 代理商： | 440EPX |
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440EPx – PPC440EPx Embedded Processor
Preliminary Data Sheet
12
AMCC Proprietary
Revision 1.26 – October 15, 2007
– Slave-terminated double word and quadword fixed length bursts
– Master-terminated variable length bursts
Guarded memory access on 4 KB boundaries
Data parity checking
Data transfers occur at PLB bus speeds.
Power management
Internal Buses
The PowerPC 440EPx features six standard internal buses: two Processor Local Buses (PLBs), three On-Chip
Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth
cores such as the PowerPC 440 processor, the DDR SDRAM memory controller, and the PCI bridge connect to
the PLBs. OPB0 hosts lower data rate peripherals. OPB1 is dedicated to USB 2.0 Device support, and OPB2 is
dedicated to USB 2.0 Host. The daisy-chained DCR provides a lower bandwidth path for passing status and
control information between the processor and the other on-chip cores.
Features include:
PLB4 (128-bit)
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
–166MHz, maximum 5.3GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1 and N:2
PLB3 (64-bit)
– 64-bit implementation of the PLB architecture
– 32-bit address
–166MHz (1:1 ratio with PLB4), maximum 1.3GB/s (no simultaneous read and write)
OPBs (OPB0, OPB1, and OPB2)
– 32-bit data path
– 32-bit address
–83MHz
DCR
– 32-bit data path
– 10-bit address
Security Function (optional)
The built-in security function (PPC440EPx-S only) is a cryptographic engine attached to the 128-bit PLB with built-
in DMA and interrupt controllers.
Features include:
Federal Information Processing Standard (FIPS) 140-2 design
Support for an unlimited number of Security Associations (SA)
Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP)
Internet Protocol Security (IPSec) features
Full packet transforms (ESP & AH)
Complete header and trailer processing (IPv4 and IPv6)
Multi-mode automatic padding
"Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
相关PDF资料 |
PDF描述 |
|---|---|
| 440EP | Power PC 440EP Embedded Processor |
| 440GP | Power PC 440GP Embedded Processor |
| 440GRX | PowerPC 440GRx Embedded Processor |
| 440GR | Power PC 440GR Embedded Processor |
| 440GX | Power PC 440GX Embedded Processor |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 440ES001B1434-4 | 功能描述:环形MIL规格后盖 CRIMIP RING ADPTR DC STRAIGHT RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440ES031M1633-3B | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRAIGHT BAND RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440ES031M2003-3B | 功能描述:环形MIL规格后盖 BND/SHRNK BOOT ADPTR DC STRAIGHT BAND RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440FA002NF1002-N | 功能描述:环形MIL规格后盖 RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
| 440FA002NF1006-N | 功能描述:环形MIL规格后盖 RoHS:否 制造商:Amphenol PCD MIL 类型:MIL-DTL-38999 III, IV 系列:AS85049 产品类型:Environmental EMI/RFI Backshells 外壳类型:Straight 外壳大小:18 外壳材质:Aluminum Alloy |
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