参数资料
型号: 403GC-3BA40C1
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 40 MHz, RISC PROCESSOR, PBGA160
封装: PLASTIC, BGA-160
文件页数: 38/48页
文件大小: 768K
代理商: 403GC-3BA40C1
IBM PowerPC 403GC
43
DMA Fly-By Continuous Burst to 3-Cycle DRAM
Bank Register Bit Settings
DMA Control Register Bit Settings
Notes:
1. DMAR must be inactive at the end of cycle 9 to guarantee three transfers.
2. Peripheral data bus width must match DRAM bus width.
3. See diagram for settings.
4. This waveform assumes that the internal address mux is used.
5. CAS0 is used for byte accesses, CAS0:1 for halfwords, and CAS0:3 for fullwords.
6. Numbers (1,2,3,...) in the DMAR signal represent when DMAR is sampled and accepted. Numbers (1,2,3,...) in the
DMAA signal represent the transfers associated with the accepted DMAR.
SLF
ERM
Bus
Width
Ext
Mux
RAS-to-
CAS
Refresh
Mode
Page
Mode
First
Access
Burst
Access
Prechg
Cycles
Refresh
RAS
Refresh
Rate
Bit 13 Bit 14
Bits
15:16
Bit 17
Bit 18
Bit 19
Bit 20
Bits
21:22
Bits
23:24
Bit 25
Bit 26
Bits
27:30
0 or 1
0
10
0
1
01
0
x
xxxx
Transfer
Direction
Transfer
Width
Transfer
Mode
Peripheral
Setup
Peripheral
Wait
Peripheral
Hold
Burst Mode
Bit 2
Bits 4:5
Bits 9:10
Bits 11:12
Bits 13:18
Bits 19-21
Bit 25
1
10
01
Note 3
xx xxxx
xxx
1
SysClk
DMAR
DMAA
A11:29
R/W
RAS
CAS0:3
DRAMOE
DRAMWE
D0:31
2
3
4
5
6
7
8
9
10
11
12
S=0
S=1
(S = peripheral setup time)
DMADXFER
Sync
BIU
Req
RAS
CAS
Pre-
Charge
Row
Column1
Column2
Column3
Data1
Data2
Data3
1
2
3
1
2
3
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