参数资料
型号: 403GC-3BA40C1
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 40 MHz, RISC PROCESSOR, PBGA160
封装: PLASTIC, BGA-160
文件页数: 27/48页
文件大小: 768K
代理商: 403GC-3BA40C1
IBM PowerPC 403GC
33
SRAM Read-Write-Read with Zero Wait and One Hold
Bank Register Bit Settings
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 19 on page 32 for WBE signal definitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of a control bit in the IOCR. When programmed
as read/write byte enables, these outputs will indicate valid bytes of the bus for both read and write operations. In
addition, the timing of these outputs will match the timing of the address bus, and the WBEON and WBEOFF
parameters will be ignored.
SLF
Burst
Mode
Bus
Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0
xx
0
00 0000
0
001
A6:29,1
WBE2[A30],
WBE3[A31]
R/W
CSx
OE
WBE0:32
D0:31
Read Address
SysClk
1
2
3
4
5
6
7
8
Data In
Data Out
Data In
Write Address
Read Address
BusError
Error?
Valid – BE
WBE0:33
Valid – BE
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