参数资料
型号: XCS30-3BG256C
厂商: Xilinx Inc
文件页数: 56/83页
文件大小: 0K
描述: IC FPGA 5V C-TEMP 256-PBGA
标准包装: 40
系列: Spartan®
LAB/CLB数: 576
逻辑元件/单元数: 1368
RAM 位总计: 18432
输入/输出数: 192
门数: 30000
电源电压: 4.75 V ~ 5.25 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 256-BBGA
供应商设备封装: 256-PBGA
Spartan and Spartan-XL FPGA Families Data Sheet
6
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
The four internal control signals are:
EC: Enable Clock
SR: Asynchronous Set/Reset or H function generator
Input 0
DIN: Direct In or H function generator Input 2
H1: H function generator Input 1.
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals. Figure 6
shows a simplified functional block diagram of the Spar-
tan/XL FPGA IOB.
IOB Input Signal Path
The input signal to the IOB can be configured to either go
directly to the routing channels (via I1 and I2 in Figure 6) or
to the input register. The input register can be programmed
as either an edge-triggered flip-flop or a level-sensitive
latch. The functionality of this register is shown in Table 3,
and a simplified block diagram of the register can be seen in
Figure 4: CLB Control Signal Interface
Multiplexer Controlled
by Configuration Program
C1
DIN
H1
SR
EC
C2
C3
C4
DS060_04_081100
Figure 5: IOB Flip-Flop/Latch Functional Block
Diagram
Table 3: Input Register Functionality
Mode
CK
EC
D
Q
Power-Up or
GSR
XX
X
SR
Flip-Flop
1*
D
0X
X
Q
Latch
1
1*
X
Q
01*
D
Both
X
0
X
Q
Legend:
XDon’t care.
Rising edge (clock not inverted).
SR
Set or Reset value. Reset is default.
0*
Input is Low or unconnected (default
value)
1*
Input is High or unconnected (default
value)
Multiplexer Controlled
by Configuration Program
DQ
Q
D
GSR
Vcc
CK
EC
SD
RD
DS060_05_041901
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