参数资料
| 型号： | XCS30-3BG256C |
| 厂商： | Xilinx Inc |
| 文件页数： | 21/83页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V C-TEMP 256-PBGA |
| 标准包装： | 40 |
| 系列： | Spartan® |
| LAB/CLB数： | 576 |
| 逻辑元件/单元数： | 1368 |
| RAM 位总计： | 18432 |
| 输入/输出数： | 192 |
| 门数： | 30000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-PBGA |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页
Spartan and Spartan-XL FPGA Families Data Sheet
28
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Slave Serial is the default mode if the Mode pins are left
unconnected, as they have weak pull-up resistors during
configuration.
Multiple slave devices with identical configurations can be
wired with parallel DIN inputs. In this way, multiple devices
can be configured simultaneously.
Serial Daisy Chain
Multiple devices with different configurations can be con-
nected together in a "daisy chain," and a single combined
bitstream used to configure the chain of slave devices.
To configure a daisy chain of devices, wire the CCLK pins of
all devices in parallel, as shown in Figure 25. Connect the
DOUT of each device to the DIN of the next. The lead or
master FPGA and following slaves each passes resynchro-
nized configuration data coming from a single source. The
header data, including the length count, is passed through
and is captured by each FPGA when it recognizes the 0010
preamble. Following the length-count data, each FPGA out-
puts a High on DOUT until it has received its required num-
ber of data frames.
After an FPGA has received its configuration data, it passes
on any additional frame start bits and configuration data on
DOUT. When the total number of configuration clocks
applied after memory initialization equals the value of the
24-bit length count, the FPGAs begin the start-up sequence
and become operational together. FPGA I/O are normally
released two CCLK cycles after the last configuration bit is
received.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The PROM File Formatter must
be used to combine the bitstreams for a daisy-chained con-
figuration.
Figure 25: Master/Slave Serial Mode Circuit Diagram
Spartan
Master
Seria
l
Spartan
Slave
FPGA
Slave
Xilinx SPROM
PROGRAM
Note:
M2, M1, M0 can be shorted
to VCC if not used as I/O
MODE
DOUT
CCLK
CLK
VCC
+5V
DATA
CE
CEO
VPP
RESET/OE
DONE
DIN
LDC
INIT
DONE
PROGRAM
D/P
INIT
RESET
CCLK
DIN
CCLK
DIN
DOUT
MODE
M1
M0
M2
(Low Reset Option Used)
3.3K
DS060_25_061301
N/C
相关PDF资料 |
PDF描述 |
|---|---|
| MPC860PVR80D4R2 | IC MPU POWERQUICC 80MHZ 357PBGA |
| IDT71T75602S133BG8 | IC SRAM 18MBIT 133MHZ 119BGA |
| IDT71T75602S100BGG8 | IC SRAM 18MBIT 100MHZ 119BGA |
| IDT71T75602S100BG8 | IC SRAM 18MBIT 100MHZ 119BGA |
| IDT71V67803S166PFG | IC SRAM 9MBIT 166MHZ 100TQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS30-3BG256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG280C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG280I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG84C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG84I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
发布紧急采购，3分钟左右您将得到回复。