参数资料
| 型号： | XCS30-3BG256C |
| 厂商： | Xilinx Inc |
| 文件页数： | 38/83页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 5V C-TEMP 256-PBGA |
| 标准包装： | 40 |
| 系列： | Spartan® |
| LAB/CLB数： | 576 |
| 逻辑元件/单元数： | 1368 |
| RAM 位总计： | 18432 |
| 输入/输出数： | 192 |
| 门数： | 30000 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-PBGA |
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Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
43
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family DC Characteristics Over Operating Conditions
Spartan Family Global Buffer Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values where one
global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB
flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Symbol
Description
Min
Max
Units
VOH
High-level output voltage @ IOH = –4.0 mA, VCC min
TTL outputs
2.4
-
V
High-level output voltage @ IOH = –1.0 mA, VCC min
CMOS outputs
VCC – 0.5
-
V
VOL
Low-level output voltage @ IOL = 12.0 mA, VCC min(1)
TTL outputs
-
0.4
V
CMOS outputs
-
0.4
V
VDR
Data retention supply voltage (below which configuration data may be lost)
3.0
-
V
ICCO
Quiescent FPGA supply current(2)
Commercial
-
3.0
mA
Industrial
-
6.0
mA
IL
Input or output leakage current
–10
+10
μA
CIN
Input capacitance (sample tested)
-
10
pF
IRPU
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 5V (sample tested)
0.02
-
mA
Notes:
1.
With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2.
With no output current loads, no active input pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a Tie
option.
Symbol
Description
Device
Speed Grade
Units
-4
-3
Max
TPG
From pad through Primary buffer, to any clock K
XCS05
2.0
4.0
ns
XCS10
2.4
4.3
ns
XCS20
2.8
5.4
ns
XCS30
3.2
5.8
ns
XCS40
3.5
6.4
ns
TSG
From pad through Secondary buffer, to any clock K
XCS05
2.5
4.4
ns
XCS10
2.9
4.7
ns
XCS20
3.3
5.8
ns
XCS30
3.6
6.2
ns
XCS40
3.9
6.7
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XCS30-3BG256I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3BG280C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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| XCS30-3BG84C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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