参数资料
型号: SI5365/66-EVB
厂商: Silicon Laboratories Inc
文件页数: 7/28页
文件大小: 0K
描述: BOARD EVAL FOR SI5365/66
标准包装: 1
主要目的: 计时,时钟发生器
已用 IC / 零件: SI5365,SI5366
已供物品: 板,线缆,CD,文档
Si5365
Rev. 0.5
15
Table 6. Si5365 Pin Descriptions
Pin #
Pin Name
I/O Signal Level
Description
1, 2, 17,
20, 23,
24, 25,
47, 48,
49, 52,
53, 72,
73, 74,
75, 90
NC
No Connect.
These pins must be left unconnected for normal operation.
3RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device registers
to their default value. Clock outputs are tristated during reset. After ris-
ing edge of RST signal, the device will perform an internal self-calibra-
tion.
This pin has a weak pullup.
4
FRQTBL
I
3-Level
Frequency Table Select.
This pin selects SONET/SDH, datacom, or SONET/SDH to datacom
frequency translation table.
L = SONET/SDH.
M= Datacom.
H = SONET/SDH to Datacom.
This pin has a weak pullup and weak pulldown and defaults to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
5, 6, 15,
27, 32,
42, 62,
63, 76,
79, 81,
84, 86,
89, 91,
94, 96,
99, 100
VDD
Supply
VDD.
The device operates from a 1.8 or 2.5 V supply. Bypass capacitors
should be associated with the following VDD pins:
Pins
Bypass Cap
5, 6
0.1 F
15
0.1 F
27
0.1 F
62, 63
0.1 F
76, 79
1.0 F
81, 84
0.1 F
86, 89
0.1 F
91, 94
0.1 F
96, 99, 100
0.1 F
7, 8, 14,
16, 18,
19, 21,
26, 28,
31, 33,
36, 38,
41, 43,
46, 51,
54, 55,
56, 64,
65
GND
Supply
Ground.
These pins must be connected to system ground. Minimize the ground
path impedance for optimal performance.
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