参数资料
型号: SI5365/66-EVB
厂商: Silicon Laboratories Inc
文件页数: 24/28页
文件大小: 0K
描述: BOARD EVAL FOR SI5365/66
标准包装: 1
主要目的: 计时,时钟发生器
已用 IC / 零件: SI5365,SI5366
已供物品: 板,线缆,CD,文档
Si5365
Rev. 0.5
5
Output Clocks (CKOUTn)3
Common Mode
CKOVCM
LVPECL 100
load line-
to-line
VDD –
1.42
—VDD –1.25
V
Differential Output
Swing
CKOVD
LVPECL 100
load line-
to-line
1.1
—
1.9
VPP
Single Ended Output
Swing
CKOVSE
LVPECL 100
load line-
to-line
0.5
—
0.93
VPP
Differential Output
Voltage
CKOVD
CML 100
load line-to-
line
350
425
500
mVPP
Common Mode Output
Voltage
CKOVCM
CML 100
load line-to-
line
—VDD-0.36
—
V
Differential Output
Voltage
CKOVD
LVDS
100
load line-to-line
500
700
900
mVPP
Low Swing LVDS
100
load line-to-line
350
425
500
mVPP
Common Mode Output
Voltage
CKOVCM
LVDS 100
load line-to-
line
1.125
1.2
1.275
V
Differential Output
Resistance
CKORD
CML, LVPECL, LVDS
—
200
—
Output Voltage Low
CKOVOLLH
CMOS
—
0.4
V
Output Voltage High
CKOVOHLH
VDD = 1.71 V
CMOS
0.8 x
VDD
——
V
Output Drive Current
(CMOS driving into
CKOVOL for output low
or CKOVOH for output
high. CKOUT+ and
CKOUT– shorted
externally)
CKOIO
VDD =1.8 V
—
7.5
—
mA
VDD =3.3 V
—
32
—
mA
Table 1. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Current draw is independent of supply voltage
2. No under- or overshoot is allowed.
3. LVPECL outputs require nominal VDD
≥ 2.5 V.
4. This is the amount of leakage that the 3-Level inputs can tolerate from an external driver. See Si53xx Family Reference
Manual for more details.
5. LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
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