参数资料
型号: LTC3546EUFD#PBF
厂商: Linear Technology
文件页数: 21/30页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 1A/2A 28QFN
标准包装: 73
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.6 V ~ 5 V
输入电压: 2.25 V ~ 5.5 V
PWM 型: 电流模式,混合
频率 - 开关: 2.25MHz,750kHz ~ 4MHz
电流 - 输出: 1A,2A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
包装: 管件
供应商设备封装: 28-QFN(4x5)
产品目录页面: 1335 (CN2011-ZH PDF)
LTC3546
APPLICATIONS INFORMATION
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage V IN drops toward V OUT , the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capabil-
ity near dropout should use a different topology such as
SEPIC, Zeta, or single inductor, positive buck boost.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in paral-
lel with C OUT , causing a rapid drop in V OUT . No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the load
switch driver. A hot swap controller is designed specifically
for this purpose and usually incorporates current limiting,
short-circuit protection, and soft starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% – (P1 + P2 + P3+…)
where P1, P2, etc. are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3546 circuits: 1) LTC3546 V IN current,
2) switching losses, 3) I 2 R losses, 4) other losses.
1. The V IN current is the DC supply current given in the
electrical characteristics which excludes MOSFET
driver and control currents. V IN current results in a
small (<0.1%) loss that increases with V IN , even at
no-load.
2. The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current re-
sults from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge moves from
V IN to ground. The resulting charge over the switching
period is a current out of V IN that is typically much larger
than the DC bias current. The gate charge losses are
proportional to V IN and thus their effects will be more
pronounced at higher supply voltages.
3. I 2 R losses are calculated from the DC resistances of
the internal switches, R SW , and the external inductor,
R L . In continuous mode, the average output current
flowing through inductor L is “chopped” between the
internal top and bottom switches. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R DS(ON) and the duty cycle
(DC) as follows:
R SW = (R DS(ON) TOP)(DC) + (R DS(ON) BOT)(1 – DC)
The R DS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I 2 R losses:
I 2 R losses = I OUT2 (R SW + R L )
Where R L is the resistance of the inductor.
4. Other hidden losses such as copper trace and inter-
nal battery resistances can account for additional ef-
ficiency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by making sure
that C IN has adequate charge storage and very low
ESR at the switching frequency. Other losses including
diode conduction losses during dead-time and inductor
core losses generally account for less than 2% total
additional loss.
Thermal Considerations
The LTC3546 requires the backplane metal (Pin 29) to be
well soldered to the PC board. This gives the UFD pack-
age exceptional thermal properties, compared to similar
packages of this size, making it difficult in normal opera-
21
For more information www.linear.com/3546
3546fc
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