参数资料
型号: IRDCIP1201-A
厂商: International Rectifier
文件页数: 17/29页
文件大小: 0K
描述: BUCK CONV REF DESIGN KIT IP1201
标准包装: 1
系列: iPOWIR™
主要目的: DC/DC,步降
输出及类型: 2,非隔离
输出电压: 1.5V,2.5V
电流 - 输出: 15A,15A
输入电压: 3.14 ~ 5.5 V
稳压器拓扑结构: 降压
频率 - 开关: 300kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: iP1201
相关产品: IP1201TRPBF-ND - IC REG BUCK SYNC ADJ 30A 198BGA
IP1201PBF-ND - IC REG BUCK SYNC ADJ 30A 198BGA
IP1201TR-ND - IC REG BUCK SYNC ADJ 30A 198BGA
IP1201-ND - IC REG BUCK SYNC ADJ 30A 198BGA
其它名称: *IRDCIP1201-A
iP1201
iP1201 Design Procedure
Only a few external components are required to com-
plete a dual output synchronous buck power supply
using iP1201. The following procedure will guide
the designer through the design and selection pro-
cess of these external components.
A typical application for iP1201 will be:
V IN = 3.3V, V OUT1 = 1.5V, I OUT1 = 10A, V OUT2 = 2.5V, I OUT2 =
6A, f sw = 200kHz, V p-p1 = V p-p2 = 40mV
Setting the Output Voltage
The output voltage of the iP1201 is set by the 0.8V
reference Vref and external voltage dividers.
Vout1
R9
FB1
nal reference source to VP-ref. In this case, to en-
sure proper start-up, power to VP-ref and iP1201
must be applied simultaneuosly.
Setting the Overvoltage Trip
Both outputs of the iP1201 will shut down if either
one of the outputs experiences a voltage in the range
of 115% of V OUT . The overvoltage sense pins FB1s
and FB2s are connected to the output through volt-
age dividers, R 13 and R 14 (Fig. 19), and the trip
setpoints are programmed according to equation
(1). Separate overvoltage sense pins FB1 s and FB2 s
are provided to protect the power supply output if for
some reason the main feedback loop is lost (for
instance, loss of feedback resistors). If this redun-
dancy is not required and if Type II control loop com-
pensation scheme is utilized, FB1s and FB2s pins
can be connected to FB1 and FB2 pins respectively.
An optional 100pF capacitor (C26) is used for delay
and filtering purposes.
In parallel configuration, FB2s should be connected to
FB1s
iP1201
FB1S
C26
(Optional)
R7
R13
R14
Setting the Soft-Start Capacitor
The soft start capacitor C ss is selected according to
equation (2):
t ss = 40 x C ss
(2)
where,
t ss is the output voltage ramp time in milliseconds,
and C ss is the soft start capacitor in μ F.
I RMS = I LOAD × D ( 1 ? D )
Fig.19: Typicalschemeforoutputvoltagesetting
V OUT1 is set according to equation (1):
V OUT1 = V ref x (1 + R 9 /R 7 ) (see Fig. 19) (1)
Setting R 7 to 1K, V OUT1 to 1.5V and Vref to 0.8V, will
result in R 9 = 875 ohms (select 887 ohms). Final
values can be selected according to the desired
accuracy of the output.
A 0.1 μ F capacitor will provide an output voltage ramp-
up time of about 4ms.
Input Capacitor Selection
The switching currents impose RMS current require-
ments on the input capacitors. The expression in
equation (3) allows the selection of the input ca-
pacitors:
(3)
where,
D is the duty cycle and is expressed as:
If the 0.8V reference is used to set the voltage for the
second output V OUT2 , VP-ref pin must be shorted to
Vref pin and in a similar way, voltage divider resis-
tors are selected for the second output V OUT2 . The
second output can also be set by applying an exter-
www.irf.com
D = V OUT / V IN .
For output1 of the above example D= 0.45 and,
I RMS = 10 x SQRT (0.45(1-0.45)) = 5A
For output2 of the above example D = 0.75 and,
17
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