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| 型号： | IRDCIP1201-A |
| 厂商： | International Rectifier |
| 文件页数： | 14/29页 |
| 文件大小： | 0K |
| 描述： | BUCK CONV REF DESIGN KIT IP1201 |
| 标准包装： | 1 |
| 系列： | iPOWIR™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.5V，2.5V |
| 电流 - 输出： | 15A，15A |
| 输入电压： | 3.14 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | iP1201 |
| 相关产品： | IP1201TRPBF-ND - IC REG BUCK SYNC ADJ 30A 198BGA IP1201PBF-ND - IC REG BUCK SYNC ADJ 30A 198BGA IP1201TR-ND - IC REG BUCK SYNC ADJ 30A 198BGA IP1201-ND - IC REG BUCK SYNC ADJ 30A 198BGA |
| 其它名称： | *IRDCIP1201-A |
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iP1201
Mode of Operation
The iP1201 can be configured to provide either two
independent dual outputs or single paralleled out-
put with current share. In dual output mode, the two
error amplifiers of the PWM controller operate inde-
pendently. Each output voltage of the iP1201 block
is controlled by its own error amplifier. The output of
the error amplifier and the internally generated ramp
signal are compared to produce PWM pulses of fixed
frequency that drive the internal power switches. In
this mode, the VP-ref pin must be connected to Vref
pin. Vref pin is the internally generated 0.8V refer-
ence input of first error amplifier . Refer to the inter-
nal block diagram of the iP1201 in Fig.1.
In single output mode, one error amplifier controls the
output voltage and the other amplifier monitors the in-
ductor current information for current sharing. In this
mode, VP-ref pin must be disconnected from Vref pin
and connected to the output of the inductor. See Fig.
17. The inductor current information is provided
through external shunts placed in series with the out-
put inductors.
A lossless inductor current sensing scheme can also
be implemented as shown in Fig. 18 where the cur-
rent is sensed throughthe DC resistance of the induc-
tor. In this case R L and C L are selected such that R L x
C L = L / R dc . Set R L = 1K and solve for C L . R dc is the
internal DC resistance of inductor L.
In single output mode, the iP1202 does not require a
soft start capacitor at SS2 pin.
The iP1201 can also be configured in dual output track-
ing mode where the second output tracks the
first output.
For a specific output configuration, follow the con-
nection diagram shown in Fig.16, Fig.17 and Fig.18
at the end of this section .
Out of Phase Operation
The dual output PWM controller inside the iP1201
provides a 180° out of phase operation of the PWM
outputs. This method of control offers the advan-
tage of reducing the amount of input bypass ca-
pacitors due to increase in input ripple frequency
and hence reduction of ripple amplitude. Moreover,
for paralleled output configurations 180° phase
shifting contributes to smaller output capacitors due
to output inductor ripple current cancellation and
ripple reduction.
14
Frequency and Synchronization
The operating switching frequency (f SW ) range ofiP1201
is 200 kHz to 400 kHz. The desired frequency is set
by placing an external resistor to the RT pin of the
iP1201. See Fig. 11 for the proper resistor value.
The iP1201 is capable of accepting an external digi-
tal synchronization signal. Synchronization will be
enabled by the rising edge clock. The free running
oscillator frequency is twice the per-channel fre-
quency. During synchronization, RT is selected such
that the free running frequency is 20% below the syn-
chronization frequency. The maximum synchroniza-
tion frequency that iP1201 can accept is 800kHz. Note
that the actual free running frequency of individual out-
put is half the synchronization frequency. Synchroni-
zation capability is provided both in independent and
parallel configurations. When unused, the SYNC pin
must be left floating.
Overcurrent Protection/Autorestart
The Overcurrent Protection function of the iP1201 of-
fers two distinct modes: HICCUP of the output and
Overcurrent Shutdown. If the Hiccup pin is pulled high
(Hiccup enabled), hiccup mode will be selected. If Hic-
cup pin is pulled low (Hiccup dis- abled), overcurrent
shutdown will be selected.
During overloads, in HICCUP disabled mode, the
controller shuts down as soon as the trip threshold
is reached. In HICCUP enabled mode, when
overcurrent trip threshold is reached, the power
supply output shuts down and attempts to restart.
The time duration between the shutdown of the
output and the restart is determined by the time it
takes to discharge the soft start capacitor. Typically,
the discharge time of the soft start capacitor is 10
times the charge time. The duty cycle of the hiccup
process is typically 5%.The output will stay in hic-
cup indefinitely until the overload is removed. The
typical overcurrent trip threshold of the device is
internally set at 20A.
Overvoltage Protection (OVP)
Overvoltage is sensed through separate output volt-
age sense pins FB1s and FB2s. A separate OVP cir-
cuit is provided for each output and the OVP thresh-
old is set to 115% of the output voltage. Upon over-
voltage condition of either one of the outputs, the OVP
forces a latched shutdown on both outputs.
www.irf.com
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