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| 型号： | IRDCIP1201-A |
| 厂商： | International Rectifier |
| 文件页数： | 13/29页 |
| 文件大小： | 0K |
| 描述： | BUCK CONV REF DESIGN KIT IP1201 |
| 标准包装： | 1 |
| 系列： | iPOWIR™ |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.5V，2.5V |
| 电流 - 输出： | 15A，15A |
| 输入电压： | 3.14 ~ 5.5 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 300kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | iP1201 |
| 相关产品： | IP1201TRPBF-ND - IC REG BUCK SYNC ADJ 30A 198BGA IP1201PBF-ND - IC REG BUCK SYNC ADJ 30A 198BGA IP1201TR-ND - IC REG BUCK SYNC ADJ 30A 198BGA IP1201-ND - IC REG BUCK SYNC ADJ 30A 198BGA |
| 其它名称： | *IRDCIP1201-A |
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iP1201
iP1201 User?s Design Guidelines
The iP1201 can be configured as a dual channel
15A or parallel single 30A power block consisting of
optimized power semiconductors, PWM control and
its associated passive components. It is based on
a synchronous buck topology and offers an optimized
solution where space, efficiency and noise caused
by parasitics are of concern. The phase shifted, two
output power block operates with fixed frequency
voltage mode control and can be configured to oper-
ate as a dual output or paralleled single output with
current sharing. The iP1201 components are inte-
grated in a ball grid array (BGA) package.
SS1/SS2
10
Css
Iss
iP1201
V IN
The input operating voltage range of the iP1201 is
3.14V to 5.5V. Both channels of the power block have
a common input.
For applications where the input bus voltage is less
than 3.5V, A and B pins should be shorted. For input
voltages greater than 3.5V, A and B pins should be
disconnected and floating. Voltages at A and B pins
are internally generated, no external voltage source
should be connected to either one of these pins. A
Power-On-Reset is performed when V IN falls below
2.5V.
Enabling the Outputs
The ENABLE pin turns on and turns off both outputs
of the iP1201 simultaneously. The iP1201 outputs
will be turned off by pulling the ENABLE pin to V IN .
ENABLE low will start the outputs. The converter can
also be shutdown by pulling the soft-start pins to
PGND through a logic level MOSFET the drain of
which connects to the soft start pin (see Fig.14).
This feature can be useful if sequencing or different
start-up timing of the outputs are required. In situa-
tions where the output has undergone a latched shut-
down due to overvoltage or overcurrent, cycling
ENABLE will reset the outputs. Cycling soft start pins
will not unlatch the outputs.
Dual Soft Start
The Soft Start function provides a controlled rise of
the output voltage, thus limiting the inrush current
during start-up. The iP1201 provides two indepen-
dent soft start functions. The soft start pins can be
connected to the soft start capacitors to provide
www.irf.com
Fig. 14: Soft Start/Enable Circuit
different start-up and sequencing profiles.
Each soft start function has an internal 25uA +/-20%
current source that charges the external soft start
capacitor C ss up to 3V. During power-up, the output
voltage starts ramping up only after the charging
voltage across the C ss capacitor has reached a
0.8Vtyp threshold, as shown in Fig. 15.
3V
0.8Vtyp
V Css
V OUT
Fig. 15: Power Up Threshold
This threshold voltage should be taken into consid-
eration when designing sequencing profiles using
the iP1201 as it will effect start-up delays and ramp-
times.
To ensure complete discharge of the soft start ca-
pacitor C ss, it is recommended to add a 1M ? resis-
tor directly across C ss .
For proper implementation of sequencing of out-
puts using the iP1201, refer to IR Application Note
AN-1053 - Power sequencing techniques using
iP1201 and iP1202.
13
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| IRDCIP1206-B | 功能描述:电源管理IC开发工具 IP1206 BUCK EVAL BRD 300kHz RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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