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| 型号： | FAN5236MTCX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DDR/PWM DUAL HE 28TSSOP |
| 产品变化通告： | Mold Compound Change 30/Nov/2007 |
| 标准包装： | 1 |
| 应用： | 控制器，移动式 DDR |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 5 V |
| 工作温度： | -10°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1221 (CN2011-ZH PDF) |
| 其它名称： | FAN5236MTCXDKR |
Design and Component Selection Guidelines
0 . 9 V V OUT ? 0 . 9 V
ESR <
Δ V
( 1 . 82 K Ω ) V OUT ? 0 . 9 ) = 3 . 24 K
Δ V =
C OUT × 8 × f SW
As an initial step, define operating input voltage range,
output voltage, and minimum and maximum load
currents for the controller.
Setting the Output Voltage
The internal reference voltage is 0.9V. The output is
divided down by a voltage divider to the VSEN pin (for
example, R5 and R6 in Figure 5). The output voltage
therefore is:
= (12)
R 6 R 5
To minimize noise pickup on this node, keep the
resistor to GND (R6) below 2K; for example, R6 at
1.82K Ω . Then choose R5:
R 5 = (13)
0 . 9
For DDR applications converting from 3.3V to 2.5V or
other applications requiring high duty cycles, the duty
cycle clamp must be disabled by tying the converter’s
FPWM to GND. When converter’s FPWM is at GND,
the converter’s maximum duty cycle is greater than
90%. When using as a DDR converter with 3.3V input,
set up the converter for in-phase synchronization by
tying the VIN pin to +5V.
Output Capacitor Selection
The output capacitor serves two major functions in a
switching power supply. Along with the inductor, it filters
the sequence of pulses produced by the switcher and it
supplies the load transient currents. The output
capacitor requirements are usually dictated by ESR,
inductor ripple current ( Δ I), and the allowable ripple
voltage ( Δ V):
(18)
Δ I
In addition, the capacitor’s ESR must be low enough to
allow the converter to stay in regulation during a load
step. The ripple voltage due to ESR for the converter in
Figure 6 is 120mV PP . Some additional ripple appears
due to the capacitance value itself:
Δ I
(19)
which is only about 1.5mV, for the converter in Figure 6,
and can be ignored.
The capacitor must also be rated to withstand the RMS
current, which is approximately 0.3 X ( Δ I), or about
400mA for the converter in Figure 6. High-frequency
decoupling capacitors should be placed as close to the
loads as physically possible .
Output Inductor Selection
(14)
Δ I = 2 × 1 MIN
=
V IN ? V OUT V OUT
I REGI = I VDDQ +
I VTT
The minimum practical output inductor value keeps
inductor current just on the boundary of continuous
conduction at some minimum load. The industry
standard practice is to choose the minimum current
somewhere from 15% to 35% of the nominal current. At
light load, the controller can automatically switch to
Hysteretic Mode of operation to sustain high efficiency.
The following equations help to choose the proper value
of the output filter inductor:
Δ V
OUT
ESR
where Δ I is the inductor ripple current and Δ V OUT is the
maximum ripple allowed:
L = × (15)
f SW × Δ I V IN
Input Capacitor Selection
The input capacitor should be selected by its ripple
current rating.
Two-Stage Converter Case
In DDR Mode (shown in Figure 5), the V TT power input
is powered by the V DDQ output; therefore, all of the input
capacitor ripple current is produced by the V DDQ
converter. A conservative estimate of the output current
required for the 2.5V regulator is:
(20)
2
As an example, if the average I VDDQ is 3A and average
I VTT is 1A, I VDDQ current is about 3.5A. If average input
voltage is 16V, RMS input ripple current is:
for this example, use:
I RMS = I OUT ( MAX ) D ? D
2
(21)
V IN = 20 , V OUT = 2 . 5
where D is the duty cycle of the PWM1 converter:
V OUT
? ? ?
?
? = 1 . 49 A
Δ I = 20 % ? 6 A = 1 . 2 A
f SW = 300 KHz
therefore:
L ≈ 6 μH
(16)
(17)
D <
V IN
therefore:
I = 3 . 5
RMS
=
2 . 5
16
16 16
2 . 5 ? 2 . 5
?
?
?
2
(22)
(23)
? 2002 Fairchild Semiconductor Corporation
FAN5236 ? Rev. 1.3.2
15
www.fairchildsemi.com
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