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| 型号： | FAN5236MTCX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 13/19页 |
| 文件大小： | 0K |
| 描述： | IC CTLR DDR/PWM DUAL HE 28TSSOP |
| 产品变化通告： | Mold Compound Change 30/Nov/2007 |
| 标准包装： | 1 |
| 应用： | 控制器，移动式 DDR |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 5 V |
| 工作温度： | -10°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1221 (CN2011-ZH PDF) |
| 其它名称： | FAN5236MTCXDKR |
f PO =
2 π R O C O
More accurate sensing can be achieved by using a
resistor (R1) instead of the R DS(ON) of the FET, as shown
in Figure 13. This approach causes higher losses, but
yields greater accuracy in both V DROOP and I LIMIT . R1 is a
low value resistor (e.g. 10m Ω ).
Current limit (I LIMIT ) should be set high enough to allow
inductor current to rise in response to an output load
transient. Typically, a factor of 1.2 is sufficient. In
addition, since I LIMIT is a peak current cut-off value,
multiply I LOAD(MAX) by the inductor ripple current (e.g.
25%). For example, in Figure 6, the target for I LIMIT :
Frequency Loop Compensation
Due to the implemented current-mode control, the
modulator has a single-pole response with -1 slope at
frequency determined by load:
1
(8)
where R O is load resistance; C O is load capacitance.
For this type of modulator, a Type-2 compensation
circuit is usually sufficient. To reduce the number of
external components and simplify the design, the PWM
I LIMIT > 1.2 x 1.25 x 1.6 x 6A
≈
14.5A
(6)
controller has an internally compensated error amplifier.
Figure 14 shows a Type-2 amplifier, its response, and
the responses of a current-mode modulator and the
Duty Cycle Clamp
During severe load increase, the error amplifier output
can go to its upper limit, pushing a duty cycle to almost
converter. The Type-2 amplifier, in addition to the pole
at the origin, has a zero-pole pair that causes a flat gain
region at frequencies between the zero and the pole.
100% for significant amount of time. This could cause a
large increase of the inductor current and lead to a long
recovery from a transient, over-current condition, or
even to a failure at especially high input voltages. To
prevent this, the output of the error amplifier is clamped
to a fixed value after two clock cycles if severe output
f Z =
f P =
1
2 π R 2 C 1
1
2 ππ 2 C 2
= 6 kHz
= 600kHz
(9)
(10)
voltage excursion is detected, limiting the maximum
duty cycle to:
This region is also associated with phase “bump” or
reduced phase shift. The amount of phase-shift
+ ? ?
?
?
DC MAX =
V OUT
V IN
? 2 . 4
? V IN
?
?
(7)
reduction depends on the width of the region of flat gain
and has a maximum value of 90°. To further simplify the
converter compensation, the modulator gain is kept
This is designed to not interfere with normal PWM
operation. When FPWM is grounded, the duty cycle
clamp is disabled and the maximum duty cycle is 87%.
Gate Driver Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive
signals, providing necessary amplification, level shifting,
and shoot-through protection. It also has functions that
optimize the IC performance over a wide range of
operating conditions. Since MOSFET switching time
can vary dramatically from type to type and with the
independent of the input voltage variation by providing
feedforward of V IN to the oscillator ramp.
The zero frequency, the amplifier high-frequency gain,
and the modulator gain are chosen to satisfy most
typical applications. The crossover frequency appears
at the point where the modulator attenuation equals the
amplifier high-frequency gain. The system designer
must specify the output filter capacitors to position the
load main pole somewhere within a decade lower than
the amplifier zero frequency. With this type of
compensation, plenty of phase margin is achieved due
to zero-pole pair phase “boost.”
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
R2
C2
C1
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than
V IN
R1
approximately 1V. Similarly, the upper MOSFET is not
turned on until the gate-to-source voltage of the lower
MOSFET has decreased to less than approximately 1V.
REF
EA Out
This allows a wide variety of upper and lower MOSFETs
to be used without a concern for simultaneous
conduction or shoot-through.
err
or
am
p
There must be a low-resistance, low-inductance path
between the driver pin and the MOSFET gate for the
adaptive dead-time circuit to function properly. Any
18
14
modul ator
delay along that path subtracts from the delay
generated by the adaptive dead-time circuit and shoot-
0
f
P0
f
Z
f
P
through may occur.
? 2002 Fairchild Semiconductor Corporation
Figure 14.
Compensation
www.fairchildsemi.com
FAN5236 ? Rev. 1.3.2
13
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| FAN5236QSC | 功能描述:开关变换器、稳压器与控制器 DC/DC RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
| FAN5236QSC_Q | 功能描述:开关变换器、稳压器与控制器 DC/DC RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
| FAN5236QSCX | 功能描述:开关变换器、稳压器与控制器 PWM Controller RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
| FAN5240 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Multi-Phase PWM Controller for AMD Mobile Athlon TM and Duron TM |
| FAN5240_06 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Multi-Phase PWM Controller for AMD Mobile Athlon and Duron |
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