参数资料
型号: XRT83SL216IB
厂商: Exar Corporation
文件页数: 15/42页
文件大小: 0K
描述: IC LIU SH E1 16CH 289STBGA
标准包装: 84
类型: 线路接口装置(LIU)
驱动器/接收器数: 16/16
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 289-LFBGA
供应商设备封装: 289-STBGA(15x15)
包装: 托盘
XRT83SL216
20
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
NOTE: VDD=3.3V ±5%, TA=25°C, Unless Otherwise Specified
2.2
HDB3 Encoder
In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3 data. If HDB3 encoding is
selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V,
where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An
example of HDB3 encoding is shown in Table 3.
2.3
Transmit Jitter Attenuator
The XRT83SL216 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed to E1 data, stuffing bits are typically removed
which can leave gaps in the incoming data stream. The JA can be configured in the transmit path with a 32-Bit
or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum gap width the
JA in the Transmit path can tolerate is shown in Table 4.
NOTE: If the LIU is used in a loop timing system, the JA should be configured in the receive path. See the Receive Section
of this datasheet.
TABLE 2: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
TCLK Duty Cycle
TCDU
30
50
70
%
Transmit Data Setup Time
TSU
50
-
ns
Transmit Data Hold Time
THO
30
-
ns
TCLK Rise Time (10% to 90%)
TCLKR
-
40
ns
TCLK Fall Time (90% to 10%)
TCLKF
-
40
ns
TABLE 3: EXAMPLES OF HDB3 ENCODING
NUMBER OF PULSES BEFORE
NEXT 4 ZEROS
Input
0000
HDB3 (Case 1)
Odd
000V
HDB3 (Case 2)
Even
B00V
TABLE 4: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS
FIFO DEPTH
MAXIMUM GAP WIDTH
32-Bit
20 UI
64-Bit
50 UI
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