参数资料
| 型号： | XRT73L03BIV |
| 厂商： | Exar Corporation |
| 文件页数： | 36/61页 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 3CH 120LQFP |
| 标准包装： | 72 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 3/3 |
| 规程： | DS3，E3，STS-1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 120-LQFP |
| 供应商设备封装： | 120-LQFP（14x20） |
| 包装： | 托盘 |
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XRT73L03B
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 1.0.1
39
Decoder detects this particular pattern, then it substi-
tutes these bits with a “0000" pattern.
Figure 25 illustrates the HDB3 Decoder at work with
two separate Zero Suppression patterns, in the in-
coming Dual-Rail Data Stream.
NOTE: If the HDB3 Decoder detects any bipolar violation
(e.g., "V") pulses that is not in accordance with the HDB3
Line Code format, or if the HDB3 Decoder detects a string
of 4 (or more) "0’s" in the incoming line signal, then the
HDB3 Decoder flags this event as a Line Code Violation by
pulsing the LCV output pin “High".
3.4.3
Configuring the HDB3/B3ZS Decoder
The XRT73L03B can enable or disable the HDB3/
B3ZS Decoder blocks by either of the following
means.
a. Operating in the HOST Mode
Enable the HDB3/B3ZS Decoder block of Channel(n)
by writing a "0" into the (SR/DR)_(n) bit-field within
Command Register CR3-(n), as illustrated below.
b. Operating in the Hardware Mode
To globally enable all HDB3/B3ZS Decoder blocks in
the XRT73L03B, pull the ENDECDIS input pin “Low".
To globally disable all HDB3/B3ZS Decoder blocks in
the XRT73L03B and configure the XRT73L03B to
transmit and receive in an AMI format, pull the END-
ECDIS input pin "High".
3.5
LOS DECLARATION/CLEARANCE
Each channel of the XRT73L03B contains circuitry
that monitors the following two parameters associat-
ed with the incoming line signals.
1. The amplitude of the incoming line signal via the
RTIP and RRing inputs.
2. The number of pulses detected in the incoming
line signal within a certain amount of time.
If a given channel of the XRT73L03B determines that
the incoming line signal is missing due to either insuf-
ficient amplitude or a lack of pulses in the incoming
line signal, it declares a Loss of Signal (LOS) condi-
tion. The channel declares the LOS condition by tog-
gling its respective RLOS_(n) output pin “High” and
by setting its corresponding RLOS_(n) bit field in
Command Register 0 or Command Register 8 to "1".
Conversely, if the channel determines that the incom-
ing line signal has been restored (e.g., there is suffi-
cient amplitude and pulses in the incoming line sig-
nal), it clears the LOS condition by toggling its re-
spective RLOS_(n) output pin "Low" and setting its
corresponding RLOS_(n) bit-field to "0".
In general, the LOS Declaration/Clearance scheme
that is employed in the XRT73L03B is based upon
FIGURE 25. AN EXAMPLE OF HDB3 DECODING
Data
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0 0
0
V
Line Signal
B
0 0
V
RPOS
RNEG
RCLK
COMMAND REGISTER CR2-(n)
D4
D3
D2
D1
D0
Reserved
ENDECDIS_(n)
ALOSDIS_(n)
DLOSDIS_(n)
REQEN_(n)
X
0X
X
1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| XRT73L03BIV-F | 功能描述:外围驱动器与原件 - PCI RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| XRT73L03IV | 制造商:EXAR 制造商全称:EXAR 功能描述:3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT |
| XRT73L03IVS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| XRT73L04A | 制造商:EXAR 制造商全称:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| XRT73L04AIV | 制造商:EXAR 制造商全称:EXAR 功能描述:4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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