参数资料
型号: XC6SLX100T-3FG484I
厂商: Xilinx Inc
文件页数: 55/89页
文件大小: 0K
描述: IC FPGA SPARTAN 6 484FGGBGA
标准包装: 60
系列: Spartan® 6 LXT
LAB/CLB数: 7911
逻辑元件/单元数: 101261
RAM 位总计: 4939776
输入/输出数: 296
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 484-BBGA
供应商设备封装: 484-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
59
Table 54: Switching Characteristics for the Delay-Locked Loop (DLL)(1)
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
Min
Max
Min
Max
Min
Max
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and
CLK180 outputs.
5
280
5
280
5
250
5
175
MHz
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and
CLK270 outputs.
5
200
5
200
5
200
5
175
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and
CLK2X180 outputs.
10
375
10
375
10
334
10
250
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output.
0.3125
186
0.3125
186
0.3125
166
0.3125
88.6
MHz
Output Clock Jitter(2)(3)(4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output.
±100
±100
±100
±100
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and
CLK2X180 outputs.
Maximum = ±[0.5% of CLKIN period + 100]
ps
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output
when performing integer division.
±150
±150
±150
±150
ps
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output
when performing non-integer
division.
Maximum = ±[0.5% of CLKIN period + 100]
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0,
CLK90, CLK180, CLK270, CLK2X,
CLK2X180, and CLKDV outputs,
including the BUFGMUX and clock
tree duty-cycle distortion.
Typical = ±[1% of CLKIN period + 350]
ps
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 1X).
±150
±150
±150
±250
ps
Phase offset between the CLKIN
and CLKFB inputs
(CLK_FEEDBACK = 2X).(6)
±250
±250
±250
±350
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
for CLK0 to CLK2X (not CLK2X180).
Maximum = ±[1% of CLKIN period + 100]
ps
Phase offset between DLL outputs
for all others.
Maximum = ±[1% of CLKIN period + 150]
Maximum =
±[1% of
CLKIN
period + 200]
ps
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