参数资料
型号: LT3587EUD#PBF
厂商: Linear Technology
文件页数: 20/24页
文件大小: 0K
描述: IC REG BOOST INV ADJ DL 20QFN
标准包装: 121
类型: 升压(升压),反相
输出类型: 可调式
输出数: 2
输出电压: 可调至 ±32V
输入电压: 2.5 V ~ 6 V
PWM 型: 电流模式
频率 - 开关: 1MHz
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
包装: 管件
供应商设备封装: 20-QFN 裸露焊盘(3x3)
产品目录页面: 1332 (CN2011-ZH PDF)
LT3587
APPLICATIONS INFORMATION
Board Layout Consideration
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize ef?ciency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential.
In order to minimize magnetic ?eld radiation, reduce the
parasitic inductance by keeping the traces that conduct high
switching currents short, wide and with minimal overall
loop area. These are typically the traces associated with
the switches. Figure 18 outlines the critical paths.
The voltage signals of the SW1, SW2 and SW3 pins have
rise and fall times of a few ns. Minimize the length and area
of all traces connected to the SW1, SW2 and SW3 pins
to reduce capacitive coupling between these fast nodes
and other circuitry. In particular, keep all the traces of the
feedback voltage pins (FB1, FB2, V FB3 and I FB3 ) away from
the switching node. Always use a ground plane under the
switching regulator to minimize interplane coupling.
Finally, place as much of the output capacitors of each
channel close to their respective CAP pins. Recommended
component placement is shown in Figure 19.
V VIN
L1
D S1
V VIN
L4
D S3
V VIN
L2
C2
L3
V NEG
SW1
SW3
SW2
C6
Q1
CAP1
LT3587
C1
C6
Q3
CAP3
LT3587
C4
C6
Q2
LT3587
GND
D S2
C7
GND
GND
Figure 18. High Current Paths
3587 F18
V IN
CAP3
C7
L4
C6
(OPT)
C4
V NEG
L3
R FB2
DS3
R IFB3
V OUT3
C FB2
C5
C2
U1
R FB1
C6
C3
V IN
DS2
DS1
C FB1
L2
C6
L1
C1
V OUT1
(OPT)
C6
(OPT)
3587 F19
V IN
CAP1
Figure 19. Recommended Component Placement
3587fc
20
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