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参数资料
| 型号： | KMPC8560VTAQFB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 32/36页 |
| 文件大小： | 0K |
| 描述： | IC MPU POWERQUICC III 783-FCPBGA |
| 标准包装： | 2 |
| 系列： | MPC85xx |
| 处理器类型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.0GHz |
| 电压： | 1.3V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 784-BBGA，FCBGA |
| 供应商设备封装： | 783-FCPBGA（29x29） |
| 包装： | 托盘 |
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MOTOROLA
MPC8560 PowerQUICC III
5
Integrated Communications Processor Product Brief
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Key Features
– Four outbound windows plus default translation for PCI
– Eight outbound windows plus default translation for RapidIO
DDR memory controller
— Programmable timing supporting DDR-1 SDRAM
— 64-bit data interface, up to 333-MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
— Contiguous or discontiguous memory mapping
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
— Sleep mode support for self-refresh SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access through JTAG port
— 2.5-V SSTL2 compatible I/O
RapidIO interface unit
— 8-bit RapidIO I/O and messaging protocols
— Source-synchronous double data rate (DDR) interfaces
— Supports small type systems (small domain, 8-bit device ID)
— Supports four priority levels (ordering within a level)
— Reordering across priority levels
— Maximum data payload of 256 bytes per packet
— Packet pacing support at the physical layer
— CRC protection for packets
— Supports atomic operations increment, decrement, set, and clear
— LVDS signaling
RapidIO–compliant message unit
— One inbound data message structure (inbox)
— One outbound data message structure (outbox)
— Supports chaining and direct modes in the outbox
— Support of up to 16 packets per message
— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message
— Supports one inbound doorbell message structure
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture.
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KMPC8567CVTANGGA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTANGJA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTANJGA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTANJJA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
| KMPC8567CVTAQGGA | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications |
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