参数资料
型号: IRDCIP1001-A
厂商: International Rectifier
文件页数: 12/18页
文件大小: 0K
描述: CONV SGL PHA SYNC BUCK 3.3-4.5V
标准包装: 1
系列: iPOWIR™
主要目的: DC/DC,步降
输出及类型: 1,非隔离
输出电压: 2V
电流 - 输出: 20A
输入电压: 3.3 ~ 4.5 V
稳压器拓扑结构: 降压
频率 - 开关: 200kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: iP1001
相关产品: IP1001TR-ND - IC REG BUCK SYNC ADJ 20A 256BGA
IP1001-ND - IC REG BUCK SYNC ADJ 20A 256BGA
其它名称: *IRDCIP1001-A
iP1001
Application Issues
Setting V OUT above 2V
In certain applications where the output voltage is
required to be set higher than the maximum DAC
code setting of 2V, it is possible to use an external
resistive voltage divider which, for accuracy, needs
to have 1% or better tolerance. The switching
frequency should be set at 200kHz by connecting
the FREQ pin to V DD . Also, the output voltage should
never be set higher than 3.3V with a V IN minimum of
5V, or 2.5V with a V IN minimum of 3.3V. The DAC
code should be set to 2V and the following equation
used to select the resistors:
V OUT = V F
x
(1 + R3/R4)
See the reference design for reference designators.
Note that the impedance at V F is 180K ? ±35%. It is
recommended that R3 be calculated assuming a
value of 1k ? for R4. Connect V FS to V F and GNDS to
PGND.
Duty Cycle D = V OUT / V IN >50%
For duty cycles >50% the switching frequency should
be set at 200kHz. 300kHz switching frequency can
be selected if the output is less than 2V and the duty
cycle is <50%.
For duty cycles >50%, add external compensation
ramp from the Vsw terminal of the iP1001 device as
shown in the reference design through R9 resistor
and C21 capacitor (Fig 10a.). For optimum perfor-
mance maintain a RC time constant of approximately
5 μ s.
12
www.irf.com
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