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| 型号： | FAN5026MTCX |
| 厂商： | Fairchild Semiconductor |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER DDR 28TSSOP |
| 产品变化通告： | Mold Compound Change 30/Nov/2007 |
| 标准包装： | 1 |
| 应用： | 控制器，DDR |
| 输入电压： | 3 V ~ 16 V |
| 输出数： | 2 |
| 输出电压： | 0.9 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1221 (CN2011-ZH PDF) |
| 其它名称： | FAN5026MTCXDKR |
I REGI = I VDDQ +
I VTT
Two-Stage Converter Case
In DDR Mode (Figure 5), the V TT power input is
powered by the V DDQ output; therefore all of the input
capacitor ripple current is produced by the V DDQ
converter. A conservative estimate of the output current
required for the 2.5V regulator is:
(18)
2
As an example, if the average I VDDQ is 3A and average
I VTT is 1A, I VDDQ current is about 3.5A. If average input
(Q G ). C ISS = C GD + C GS and it controls t1, t2, and t4
timing. C GD receives the current from the gate driver
during t3 (as V DS is falling). The gate charge (Q G )
parameters on the lower graph are either specified in or
can be derived from MOSFET datasheets.
Assuming switching losses are about the same for both
the rising edge and falling edge, Q1’s switching losses
occur during the shaded time when the MOSFET has
voltage across it and current through it.
These losses are given by:
P UPPER = P SW + P COND (25)
I RMS = I OUT ( MAX ) D ? D
× I L
P SW = ? DS
?
?
× 2 × t s ? f SW
?
voltage is 16V, RMS input ripple current is:
2
(19)
? V
2
?
?
(26)
V OUT 2 . 5
V IN
where D is the duty cycle of the PWM1 converter and:
D < = (20)
12
P COND =
where:
V OUT
V IN
× I OUT 2 × R DS ( ON )
(27)
I RMS
? 2 . 5
? ?
? 12
? = 1 . 42 A
therefore:
= 3 . 5
2 .5
12
?
?
?
?
2
(21)
P UPPER is the upper MOSFET’s total losses and P SW
and P COND are the switching and conduction losses for a
given MOSFET;
R DS(ON) is at the maximum junction temperature (T J );
and
Dual Converter 180° Phased
In Dual Mode (shown in Figure 5), both converters
contribute to the capacitor input ripple current. With
each converter operating 180° out of phase, the RMS
currents add in the following fashion:
t S is the switching period (rise or fall time), shown as t2
and t3 in Figure 16.
The driver’s impedance and C ISS determine t2, while
t3’s period is controlled by the driver’s impedance and
Q GD . Since most of t S occurs when V GS = V SP , use a
constant current assumption for the driver to simplify
= I
+ I
I
or
RMS RMS ( 1 ) RMS ( 2 )
2 2
( (
I RMS = ( I 1 ) 2 D 1 ? D 1 2 ) + ( I 2 ) 2 D 2 ? D 2 2 )
(22)
(23)
the calculation of t S :
C ISS
V DS
C GD
C ISS
which, for the dual 3A converters of Figure 6, calculates:
I RMS = 1 . 51 A
Power MOSFET Selection
(24)
I D
Losses in a MOSFET are the sum of its switching (P SW )
and conduction (P COND ) losses.
In typical applications, the FAN5026 converter’s output
voltage is low with respect to its input voltage.
Therefore, the lower MOSFET (Q2) is conducting the
V SP
Q GS
Q GD
4.5V
full load current for most of the cycle. Q2 should
therefore be selected to minimize conduction losses,
thereby selecting a MOSFET with low R DS(ON) .
V TH
V GS
t1
t2
Q G(SW)
t3
t4
t5
In contrast, the high-side MOSFET (Q1) has a much
shorter duty cycle and it’s conduction loss has less
impact. Q1, however, sees most of the switching losses,
the primary selection criteria should be gate charge.
Figure 16.
5V
Switching Losses and Q G
C GD
VIN
High-Side Losses
Figure 16 shows a MOSFET’s switching interval, with
R D
HDRV
G
R GATE
the upper graph being the voltage and current on the
drain-to-source and the lower graph detailing V GS vs.
time with a constant current charging the gate. The X
axis, therefore, is also representative of gate charge
Figure 17.
C GS
SW
Drive Equivalent Circuit
? 2005 Fairchild Semiconductor Corporation
FAN5026 ? Rev. 1.0.8
14
www.fairchildsemi.com
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