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参数资料
| 型号： | DSPB56725CAF |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 48/48页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 80LQFP |
| 标准包装： | 90 |
| 系列： | DSP56K/Symphony |
| 类型： | 音频处理器 |
| 接口： | 主机接口，I²C，SAI，SPI |
| 时钟速率： | 200MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 112kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.00V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
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Symphony DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2
Freescale Semiconductor
9
1.1.6
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8 V and a VIH
minimum of 2.0 V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in
production with respect to the 50% point of the respective input signal’s transition. For all pins, output levels are measured with
the production test machine VOL and VOH reference levels set at 0.4 V and 2.4 V, respectively.
1.1.7
Internal Clocks
Table 5 lists the internal clocks.
Internal supply current1 (core only) operating at
Fsys < 250 MHz
In Normal mode
ICCI
—
140
340
mA
In Wait mode
ICCW
—90
290
mA
In Stop mode2
ICCS
—40
240
mA
Input capacitance
CIN
—
10
pF
Note:
1. The Current Consumption section provides a formula to compute the estimated current requirements in Normal mode. In
order to obtain these results, all inputs must be terminated (for example, not allowed to float). Measurements are based on
synthetic intensive DSP benchmarks. The power consumption numbers in this specification are 90% of the measured
results of this benchmark. This reflects typical DSP applications. Typical internal supply current with Fsys < 200 MHz is
measured with VCORE_VDD = 1.0 V, VDD_IO = 3.3 V at TJ = 25° C. Maximum internal supply current is measured with
VCORE_VDD = 1.05 V, VIO_VDD) = 3.6 V at TJ = 100° C. Typical internal supply current with Fsys < 250 MHz is measured with
VCORE_VDD = 1.2 V, VDD_IO = 3.3 V at TJ = 25° C. Maximum internal supply current is measured with VCORE_VDD = 1.26 V,
VIO_VDD) = 3.6 V at TJ = 90° C.
2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (that is, not allowed
to float).
Table 5. Internal Clocks
No.
Characteristics
Symbol
Min
Typ
Max
Unit
Condition
1
Comparison Frequency
Fref
2
—
8
MHz
Fref = Fin/NR
2
Input Clock Frequency
with PLL enabled
with PLL disabled
Fin
2
—
248
200
MHz
—
Table 4. DC Electrical Characteristics (Continued)
Characteristics
Symbol
Min
Typ
Max
Unit
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