参数资料
| 型号： | CAT9555YI-T2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 16B 24TSSOP |
| 标准包装： | 1 |
| 接口： | I²C，串行，SMBus |
| 输入/输出数： | 16 |
| 中断输出： | 是 |
| 频率 - 时钟： | 400kHz |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 标准包装 |
| 包括： | POR |
| 产品目录页面： | 807 (CN2011-ZH PDF) |
| 其它名称： | CAT9555YI-T2DKR |
CAT9555
http://onsemi.com
11
Power-On Reset Operation
When the power supply is applied to VCC pin, an internal power-on reset pulse holds the CAT9555 in a reset state until VCC
reaches VPOR level. At this point, the reset condition is released and the internal state machine and the CAT9555 registers are
initialized to their default state.
SA
1 0
0 0
A0
0 1
AA
COMMAND BYTE
acknowledge
from slave
acknowledge
from slave
A
P
NA
acknowledge
from slave
acknowledge
from master
S
DATA
first byte
last byte
no acknowledge
from master
1
slave address
data from upper
or lower byte of
register
data from lower
or upper byte
of register
slave address
MSB
LSB
MSB
LSB
0
Figure 12. Read from Register
NOTE: Transfer can be stopped at any time by a STOP condition.
R/W
A2 A1
R/W
A2 A1 A0
at this moment mastertransmitter
becomes masterreceiver and
slavereceiver becomes
slavetransmitter
Figure 13. Read Input Port Register
12 3 4 5 6 7 8 9
S0 10 0 A2A1A0 1 A
A
I0.x
A
I1.x
A
I0.x
1
I1.x
P
SCL
SDA
ACKNOWLEDGE
NON ACKNOWLEDGE
FROM MASTER
READ FROM PORT 0
READ FROM
DATA INTO PORT 1
DATA 00
DATA 10
DATA 12
tIR
tIV
INT
tps
DATA 11
tph
DATA 03
tps
DATA 02
FROM MASTER
ACKNOWLEDGE
FROM MASTER
DATA 03
R/W
ACKNOWLEDGE
FROM MASTER
ACKNOWLEDGE
FROM SLAVE
tph
DATA 01
DATA 00
DATA 10
DATA INTO PORT 0
NOTE: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to 00 (read input port register).
PORT 1
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