参数资料
| 型号： | CAT9555YI-T2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 16B 24TSSOP |
| 标准包装： | 1 |
| 接口： | I²C，串行，SMBus |
| 输入/输出数： | 16 |
| 中断输出： | 是 |
| 频率 - 时钟： | 400kHz |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 标准包装 |
| 包括： | POR |
| 产品目录页面： | 807 (CN2011-ZH PDF) |
| 其它名称： | CAT9555YI-T2DKR |
CAT9555
http://onsemi.com
9
Registers and Bus Transactions
The CAT9555 internal registers and their address and
function are shown in Table 7.
The command byte is the first byte to follow the device
address byte during a write/read bus transaction. The
register command byte acts as a pointer to determine which
register will be written or read.
The input port register is a read only port. It reflects the
incoming logic levels of the I/O pins, regardless of whether
the pin is defined as an input or an output by the configuration
register. Writes to the input port register are ignored.
Table 7. REGISTER COMMAND BYTE
Command (hex)
Register
0h
Input Port 0
1h
Input Port 1
2h
Output Port 0
3h
Output Port 1
4h
Polarity Inversion Port 0
5h
Polarity Inversion Port 1
6h
Configuration Port 0
7h
Configuration Port 1
Table 8. REGISTERS 0 AND 1 – INPUT PORT REGISTERS
bit
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
default
X
bit
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
default
X
Table 9. REGISTERS 2 AND 3 – OUTPUT PORT REGISTERS
bit
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
default
1
bit
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
default
1
Table 10. REGISTERS 4 AND 5 – POLARITY INVERSION REGISTERS
bit
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
default
0
bit
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
default
0
Table 11. REGISTERS 6 AND 7 – CONFIGURATION REGISTERS
bit
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
default
1
bit
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
default
1
Figure 9. Acknowledge Timing
18
9
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER)
ACK DELAY
ACK SETUP
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
(≥ tSU:DAT)
(≤ tAA)
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