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参数资料
| 型号： | BD9141MUV-E2 |
| 厂商： | Rohm Semiconductor |
| 文件页数： | 14/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2A 20VQFN |
| 产品培训模块： | High Efficiency Current Mode Switching Regulators CMOS LDO Regulators |
| 特色产品： | BD91x Series Step-Down Regulators |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 2.5 V ~ 6 V |
| 输入电压： | 4.5 V ~ 13.2 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 2A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | VQFN020V4040 |
| 产品目录页面： | 1373 (CN2011-ZH PDF) |
| 其它名称： | BD9141MUV-E2DKR |
BD9141MUV
Datasheet
V CC
Cin
EN
V CC ,PV CC
SW
L
V OUT
V OUT
V OUT
ITH
GND,PGND
ESR
C O
R O
R ITH
C ITH
Fig.33 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
fz (Amp.) = fp (Min.)
1
2 π× R ITH × C ITH
5. Determination of output voltage
=
1
2 π× R OMax. × C O
The output voltage V OUT is determined by the equation (6):
V OUT =(R2/R1+1) × V ADJ ??? (6) V ADJ : Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
SW
L
Co
R2
Output
Adjustable output voltage range : 2.5V to 6.0V
ADJ
R1
Fig.34 Determination of output voltage
Use 1 k? to 100 k? resistor for R1. if you can use the resistance more than
100k Ω or they have a big range between the setting value of output voltage and
input voltage.
8
7.5
Vo=6.0V
The minimum input voltage depends on the setting output voltage.
Basically, it is recommended to use in the condition :
V CCmin = V OUT +1.3V.
It is shown the necessary output current value at the minimum
input voltage. (DCR of inductor : 0.1Ω)See Fig.35.
This data is the characteristic value, so it doesn ’t guarantee the
operation range.
7
6.5
6
5.5
5
Vo=5.0V
Vo=4.0V
Vo=3.3V
6.Selection of the reference voltage capacitor (C VREG )
VREG voltage is the reference voltage created by Input voltage (Vcc
Voltage). C VREG capacitor should be selected 0.1μF or more.
4.5
0 0.5 1 1.5 2
OUTPUT CURRENT : IOUT[A]
Fig.35 minimum input voltage in each output voltage
www.rohm.com
?2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
14/19
TSZ02201-0J3J0AJ00180-1-2
02.MAR.2012 Rev.001
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