参数资料
型号: A3998SETTR-T
厂商: Allegro Microsystems Inc
文件页数: 11/20页
文件大小: 0K
描述: IC MOTOR DRIVER DUAL DMOS QFN
标准包装: 1
应用: 直流电机驱动器,PWM 电机驱动器,步进电机驱动器
输出数: 1 或 2
电流 - 输出: ±1.5A
电压 - 负载: 9 V ~ 50 V
电源电压: 3 V ~ 5.5 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN
包装: 标准包装
其它名称: 620-1459-6
A3998
Protection
Switching Regulator The buck switch is disabled under the fol-
lowing fault conditions:
? V BB < V BBUV(th)
? V CP < V BB + 5 V
? Thermal shutdown fault
Thermal Protection A thermal shutdown circuit turns-off all
drivers and disables the switching regulator in the event of a fault
due to excessive junction temperature. The serial port Configura-
tion register is not reset.
Shutdown occurs when the junction temperature reaches T JSD ,
165°C (typ). Thermal shutdown has a hysteresis, T JSDHYS , of
approximately 20°C (typ). The outputs of the device remain dis-
abled until the fault condition is removed.
PMON Pin Open drain output, logic high indicates V BB is above
the UVLO threshold.
Undervoltage Lockout At power-up, and in the event of low
V IN , the UVLO circuit disables the drivers and the serial port
Configuration register is reset to the default, POR state.
OCP When an overcurrent event is detected, the serial port
Configuration register is reset to the default (POR) state. This
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
fault is latched and can only be reset by cycling the power to the
A3998 ( power-on reset, POR) or by cycling Standby mode (via
the SLEEPN pin).
Note: An overcurrent fault event will not be generated during a
shorted load condition if the blank time is programmed shorter
than the t OCP . In this case, the overcurrent protection is still
active, however, the internal current control circuit will operate as
normal and terminate the source driver on-state upon completion
of the blank time, before the OCP can trip the fault line and reset
the serial port.
Power-On Reset
FRST Pin Active high input signal forces reset (POR).
RSTN Pin An open drain output, RSTN will be low if either of
following conditions are true:
? V FB1 < V FBUV(th)
? FRST high
If neither of the conditions are true, there will be a 100 ms delay
before RSTN goes high. (See RST Function with FRST Input
timing diagram.)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
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