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参数资料
| 型号： | A3998SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRIVER DUAL DMOS QFN |
| 标准包装： | 1 |
| 应用： | 直流电机驱动器，PWM 电机驱动器，步进电机驱动器 |
| 输出数： | 1 或 2 |
| 电流 - 输出： | ±1.5A |
| 电压 - 负载： | 9 V ~ 50 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN |
| 包装： | 标准包装 |
| 其它名称： | 620-1459-6 |
A3998
Phase Control
This setting sets the relative states of the full-bridge outputs. This
determines if the device operates in the forward or reverse (rela-
tive) direction:
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
Blank Time Two bits (word 0/1, D1:D0) are available for each
full bridge to set the current sense comparator blank time when
any output driver is switched on. The settings are according to the
following table (T OSC is the period of the internal oscillator):
Serial Port
Configuration Bit
(Word 2)
Phase
Serial Port Configuration Bit
(Word 0/1)
Blank Time
D2/D9
State
OUTA
OUTB
D1
D0
0
1
Reverse
Forward
Low
High
High
Low
0
0
0
1
4 × T OSC
6 × T OSC
1
0
12 × T OSC
Enable Logic
1
1
24 × T OSC
The ENB1 and ENB2 input terminals are provided for external
PWM control of the two full bridges. When ENBx is set to logic
high, output on the corresponding full bridge is enabled. When
set to logic low, the bridge output is chopped.
Fast Decay Time
Four bits (word 0/1, D10:D7) are available for each full bridge to
set the Fast Decay portion, t FD , of the fixed off-time when Inter-
nal PWM control, Mixed Decay mode is selected.
The Fast Decay portion is defined by:
t FD = (1 + N ) × T OSC × 8 – T OSC (4)
where N is the word value, from 0 to 15.
For example, given the internal oscillator frequency, f OSC , of
4 MHz (typ) (T OSC = 250 ns), the fixed off-time is adjustable
from 2 to 32 μ s in increments of 2 μ s. For t FD > t OFF , the device
effectively operates in Fast Decay mode.
PWM Blank Timer
When a source driver turns on, a current spike occurs due to the
reverse recovery currents of the clamp diodes and/or switch-
ing transients related to distributed capacitance in the load. To
prevent this current spike from erroneously resetting the source
enable latch, the sense comparator is blanked.
The programmable blanking function is enabled while the blank
timer runs, which is after the off-time counter expires. When the
Enable (ENBx) signal is chopped, or the Phase setting in the the
Configuration register is changed, a PWM-off cycle is initiated
and the blank timer is reset.
For example, given the internal oscillator frequency, f OSC , of
4 MHz (typ) (T OSC = 250 ns), the blank time is adjustable from
1 to 6 μ s.
Synchronous Rectification
When a PWM-off cycle is triggered, either by an Enable chop
command or an Internal PWM control mode Fixed Off-Time
cycle, the load current recirculates according to the decay mode
selected by the Configuration register settings. After a short
crossover delay, the synchronous rectification feature turns-on the
appropriate MOSFET (or pair of MOSFETs, for the Mixed Decay
portion of the off-time) during the current decay and effectively
shorts-out the body diodes with the low R DS(on) driver. This low-
ers power dissipation significantly and can eliminate the require-
ment for external Schottky diodes.
Synchronous rectification can be configured in active mode or
passive mode via the serial port (word 0/1, D11):
? Active mode prevents reversal of load current by turning-off
synchronous rectification when a zero current level is detected.
? Passive mode allows reversal of current, but turns-off synchro-
nous rectification if the load current inversion ramps up to the
I TRIP current limit (see equation 1).
SLEEPN Pin Active low input signal to reset serial port Configu-
ration register and enter Standby mode. During Standby mode,
the regulators can still operate.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
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