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参数资料
| 型号： | 70T631S12DDGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 12 ns, PQFP144 |
| 封装： | 20 X 20 MM, 1.40 MM HIEGHT, GREEN, TQFP-144 |
| 文件页数： | 4/27页 |
| 文件大小： | 220K |
| 代理商： | 70T631S12DDGI |
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IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
Timing of Power-Up Power-Down
Waveform of Read Cycles(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE, CE, LB or UB.
2. Timing depends on which signal is de-asserted first
CE, OE, LB or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA, tABE, or tBDD.
5.
SEM = VIH.
6.
CE = L occurs when CE0 = VIL and CE1 = VIH. CE = H when CE0 = VIH and/or CE1 = VIL.
tRC
R/
W
CE
ADDR
tAA
OE
UB, LB
5670 drw 06
(4)
tACE
(4)
tAOE
(4)
tABE
(4)
tOH
(2)
tHZ
(3,4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
(6)
.
(1)
tLZ/tLZOB
CE
5670 drw 07
tPU
ICC
ISB
tPD
50%
.
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