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参数资料
| 型号： | 70P249L65BYGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | SRAM |
| 英文描述： | 4K X 16 DUAL-PORT SRAM, 40 ns, PBGA100 |
| 封装： | 0.50 MM PITCH, GREEN, BGA-100 |
| 文件页数： | 22/22页 |
| 文件大小： | 146K |
| 代理商： | 70P249L65BYGI |
6.42
9
IDT70P269/259/249L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM
Industrial Temperature Range
OCTOBER 16, 2008
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
Symbol
Parameter
70P269/259/249
Unit
65 ns
90 ns
Min.
Max.
Min.
Max..
ADM Port Read Cycle (2)
tRC
Read Cycle Time
65
____
90
____
ns
tACC1
Random Access
ADV Low to Data Valid
____
65
____
90
ns
tACC2
Random Access Address to Data Valid
____
65
____
90
ns
tACC3
Random Access
CS to Data Valid
____
65
____
90
ns
tAVDA
Random Access
ADV High to Data Valid
____
35
____
50
ns
tAVD
ADV Low Pulse
15
____
20
____
ns
tAVDS
Address Set-up to
ADV Rising Edge
15
____
20
____
ns
tAVDH
Address Hold from
ADV Rising Edge
3
____
5
____
ns
tCSS
CS Set-up to ADV Rising Edge
7
____
10
____
ns
tOE
OE Low to Data Valid
____
35
____
50
ns
tLZOE(3)
OE Low to I/O Low-Z
3
____
5
____
ns
tHZOE(3)
OE High to I/O High-Z
____
15
____
25
ns
tHZCS(3)
CS High to I/O High-Z
____
15
____
25
ns
tDBE
UB/LB Low to I/O Valid
____
35
____
50
ns
tLZBE(3)
UB/LB Low to I/O Low-Z
3
____
5
____
ns
tHZBE(3)
UB/LB High to I/O High-Z
____
15
____
25
ns
tAVOE
ADV High to OE Low
0
____
0
____
ns
tPU
Chip Enable to Power Up Time
0
____
0
____
ns
tPD
Chip Disable to Power Down Time
____
65
____
90
ns
Standard Port Read Cycle (4)
tRC
Read Cycle Time
40
____
60
____
ns
tAA
Address to Data Valid
____
40
____
60
ns
tOHA
Output Hold from Address Change
5
____
5
____
ns
tACS
CS to Data Valid
____
40
____
60
ns
tDOE
OE Low to Data Valid
____
25
____
35
ns
tLZOE(3)
OE Low to Data Low-Z
5
____
5
____
ns
tHZOE(3)
OE High to Data High-Z
____
10
____
30
ns
tLZCS(3)
CS Low to Data Low-Z
5
____
5
____
ns
tHZCS(3)
CS Low to Data High-Z
____
10
____
30
ns
tLZBE(3)
UB/LB Low to Data Low-Z
5
____
5
____
ns
tHZBE(3)
UB/LB High to Data High-Z
____
10
____
30
ns
tABE
UB/LB Access Time
____
40
____
60
ns
7146 tbl 12
NOTES:
1. VDD = 1.8V
2. ADM port timing applies to the left or right port when configured to ADM mode.
3. This parameter is guaranteed by design and is not tested.
4. Standard SRAM port timing applies to the left or right port when configured to standard SRAM mode.
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