参数资料
型号: 4307-52
厂商: Peregrine Semiconductor
文件页数: 8/11页
文件大小: 0K
描述: IC DSA 5BIT 75 OHM 20-QFN
标准包装: 1
系列: UltraCMOS™
衰减值: 15.5dB
容差: ±0.15dB
频率范围: 0 ~ 2GHz
阻抗: 75 欧姆
封装/外壳: 20-WFQFN 裸露焊盘
其它名称: 1046-1034-6
PE4307
Product Specification
Figure 18. Serial Interface Timing Diagram
LE
Table 7. 5-Bit Attenuator Serial Programming
Register Map
Clock
B5
0
B4
C8
B3
C4
B2
C2
B1
C1
B0
C0.5
?
?
Data
MSB
LSB
MSB (first in)
LSB (last in)
t SDSUP
t SDHLD
t LESUP
t LEPW
Note: The start bit (B5) must always be low to prevent an unknown state in the
device
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data
C8:C0.5
t PDSUP
t LEPW
t PDHLD
Table 8. Serial Interface AC Characteristics
V DD = 3.0V, -40°C < T A < 85°C, unless otherwise specified
Table 9. Parallel Interface AC Characteristics
V DD = 3.0V, -40°C < T A < 85°C, unless otherwise specified
Symbol
Parameter
Min
Max
Unit
Symbol
Parameter
Min
Max
Unit
f Clk
t ClkH
t ClkL
t LESUP
Serial data clock
frequency (Note 1)
Serial clock HIGH time
Serial clock LOW time
LE set-up time after last
clock falling edge
30
30
10
10
MHz
ns
ns
ns
t LEPW
t PDSUP
t PDHLD
LE minimum pulse width
Data set-up time before
rising edge of LE
Data hold time after
falling edge of LE
10
10
10
--
--
--
ns
ns
ns
t LEPW
t SDSUP
t SDHLD
LE minimum pulse width
Serial data set-up time
before clock rising edge
Serial data hold time
after clock falling edge
30
10
10
ns
ns
ns
Note 1: f Clk is verified during the functional pattern test. Serial programming
sections of the functional pattern are clocked at 10 MHz to verify fclk
specification
?2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0161-05 │ UltraCMOS ? RFIC Solutions
Page 8 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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