参数资料
型号: 4307-52
厂商: Peregrine Semiconductor
文件页数: 2/11页
文件大小: 0K
描述: IC DSA 5BIT 75 OHM 20-QFN
标准包装: 1
系列: UltraCMOS™
衰减值: 15.5dB
容差: ±0.15dB
频率范围: 0 ~ 2GHz
阻抗: 75 欧姆
封装/外壳: 20-WFQFN 裸露焊盘
其它名称: 1046-1034-6
PE4307
Product Specification
Figure 15. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
V DD
V I
Parameter/Condition
Power supply voltage
Voltage on any input
Min
-0.3
-0.3
Max
4.0
V DD +
0.3
Unit
V
V
N/C
1
15
C8
T ST
Storage temperature range
-65
150
°C
RF1
Data
Clock
2
3
4
20-lead
QFN
4x4mm
Exposed Solder Pad
14
13
12
RF2
P/S
Vss/GND
P IN
V ESD
Input power (50 ? )
ESD voltage (Human Body
Model)
+30
500
dBm
V
LE
5
11
GND
Table 4. Operating Ranges
Table 2. Pin Descriptions
Parameter
V DD Power Supply
Voltage
I DD Power Supply
Current
Min
2.7
Typ
3.0
Max
3.3
100
Unit
V
μ A
Pin No.
1
2
3
4
Pin
Name
N/C
RF1
Data
Clock
Description
No connect
RF port (Note 1)
Serial interface data input (Note 4)
Serial interface clock input
Digital Input High
Digital Input Low
Digital Input Leakage
Input Power
Temperature range
0.7xV DD
-40
0.3xV DD
1
+24
85
V
V
μ A
dBm
°C
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LE
V DD
N/C
PUP2
V DD
GND
GND
V ss /GND
P/S
RF2
C8
C4
C2
GND
C1
C0.5
Latch Enable input (Note 2)
Power supply pin
No connect
Power-up selection bit
Power supply pin
Ground connection
Ground connection
Negative supply voltage or GND
connection (Note 3)
Parallel/Serial mode select
RF port (Note 1)
Attenuation control bit, 8 dB
Attenuation control bit, 4 dB
Attenuation control bit, 2 dB
Ground connection.
Attenuation control bit, 1 dB
Attenuation control bit, 0.5 dB
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS ? device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS ?
devices are immune to latch-up.
Paddle GND Ground for proper operation
Notes: 1. Both RF ports must be held at 0 V DC or DC blocked with an external
series capacitor
2. Latch Enable (LE) has an internal 100 k ? resistor to V DD
3. Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V SS (-V DD ) to bypass and disable
internal negative voltage generator
4. Place a 10 k ? resistor in series, as close to pin as possible to avoid
frequency resonance. See “Resistor on 3” paragraph
?2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Switching Frequency
The PE4307 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 k ? resistor on the input to Pin 3 (see Figure 5 )
will eliminate package resonance between the RF
input pin and the digital input. Specified attenuation
error versus frequency performance is dependent
upon this condition.
Document No. 70-0161-05 │ UltraCMOS ? RFIC Solutions
Page 2 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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