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参数资料
| 型号： | 4305-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 8/11页 |
| 文件大小： | 0K |
| 描述： | IC DSA 5BIT 50 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 15.5dB |
| 容差： | ±0.25dB |
| 频率范围： | 0 ~ 4GHz |
| 阻抗： | 50 欧姆 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 其它名称： | 1046-1032-6 |
PE4305
Product Specification
Figure 17. Serial Interface Timing Diagram
Table 7. 5-Bit Attenuator Serial Programming
Register Map
LE
Clock
B5
0
B4
C8
B3
C4
B2
C2
B1
C1
B0
C0.5
↑
↑
Data
MSB
LSB
MSB (first in)
LSB (last in)
t SDSUP
t SDHLD
t LESUP
t LEPW
Note: The start bit (B5) must always be low to prevent the attenuator
from entering an unknown state.
Figure 18. Parallel Interface Timing Diagram
LE
Parallel Data
C8:C0.5
t PDSUP
t LEPW
t PDHLD
Table 8. Serial Interface AC Characteristics
V DD = 3.0 V, -40° C < T A < 85° C, unless otherwise specified
Table 9. Parallel Interface AC Characteristics
V DD = 3.0 V, -40° C < T A < 85° C, unless otherwise specified
Symbol
f Clk
t ClkH
t ClkL
Parameter
Serial data clock
frequency (Note 1)
Serial clock HIGH time
Serial clock LOW time
Min
30
30
Max
10
Unit
MHz
ns
ns
Symbol
t LEPW
t PDSUP
t PDHLD
Parameter
LE minimum pulse width
Data set-up time before
rising edge of LE
Data hold time after
falling edge of LE
Min
10
10
10
Max
Unit
ns
ns
ns
t LESUP
t LEPW
t SDSUP
t SDHLD
LE set-up time after last
clock falling edge
LE minimum pulse width
Serial data set-up time
before clock rising edge
Serial data hold time
after clock falling edge
10
30
10
10
ns
ns
ns
ns
Note: f Clk is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked at
10 MHz to verify fclk specification.
?2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0159-06 │ UltraCMOS? RFIC Solutions
Page 8 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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