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| 型号： | 4305-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC DSA 5BIT 50 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 15.5dB |
| 容差： | ±0.25dB |
| 频率范围： | 0 ~ 4GHz |
| 阻抗： | 50 欧姆 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 其它名称： | 1046-1032-6 |
PE4305
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4305 DSA.
J9 is used in conjunction with the supplied DC cable
to supply VDD, GND, and –VDD. If use of the
internal negative voltage generator is desired, then
connect –VDD (black banana plug) to ground. If an
external –VDD is desired, then apply -3V.
J1 should be connected to the LPT1 port of a PC
with the supplied control cable. The evaluation
software is written to operate the DSA in serial
mode, so switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation setting
to the desired combined attenuation. The software
automatically programs the DSA each time an
attenuation state is enabled or disabled.
To evaluate the Power Up options, first disconnect
the control cable from the evaluation board. The
control cable must be removed to prevent the PC
port from biasing the control pins.
During power up with P/S=1 high and LE=0 or P/S=0
low and LE=1, the default power-up signal
attenuation is set to the value present on the five
control bits on the five parallel data inputs (C0.5 to
C8). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
Figure 15. Evaluation Board Layout
Peregrine Specification 101/0112
Figure 16. Evaluation Board Schematic
Peregrine Specification 102/0144
During power up with P/S=0 high and LE=0, the
C0.5
C1
C2 C4
control bits are automatically set to one of two
possible values presented through the PUP
interface. These two values are selected by the
J4
1
N/C
C8
15
C8
J5
power-up control bit, PUP2, as shown in Table 6.
Pins 1 and 7 are open and may be connected to any
bias.
SMA
1
DATA
Z=50 Ohm
10 kohm
CLK
2
3
4
RFin
DATA
CLK
U1
QFN4X4
RFout
PS
VNEG
14
13
12
PS
Z=50 Ohm
1
SMA
Resistor on Pin 3
LE
5
LE
GND
11
A 10 k ? resistor on the input to pin 3 (Figure 16) will
eliminate package resonance between the RF input
pin and the digital input. Specified attenuation error
VCC
PUP2
versus frequency performance is dependent upon
this condition.
100 pF
Note: Resistor on pin 3 is required and should be placed as close to
the part as possible to avoid package resonance and meet error
specifications over frequency.
Document No. 70-0159-06 │ www.psemi.com
?2003-2008 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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