参数资料
型号: XRT83VSH314IB
厂商: Exar Corporation
文件页数: 67/80页
文件大小: 0K
描述: IC LIU SH T1/E1/J1 14CH 304TBGA
标准包装: 27
类型: 线路接口装置(LIU)
驱动器/接收器数: 14/14
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 304-BBGA
供应商设备封装: 304-PBGA(31x31)
包装: 托盘
XRT83VSH314
4
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
1.0
PIN DESCRIPTIONS
MICROPROCESSOR
NAME
PIN
TYPE
DESCRIPTION
CS
A22
I
Chip Select Input
Active low signal. This signal enables the microprocessor interface by pulling
chip select "Low". The microprocessor interface is disabled when the chip
select signal returns "High".
NOTE: Internally pulled "High" with a 50k
resistor.
ALE_TS
C19
I
Address Latch Enable Input (Transfer Start)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k
resistor.
WR_R/W
A20
I
Write Strobe Input (Read/Write)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k
resistor.
RD_WE
D18
I
Read Strobe Input (Write Enable)
See the Microprocessor section of this datasheet for a description.
NOTE: Internally pulled "Low" with a 50k
resistor.
RDY_TA
AA3
O
Ready Output (Transfer Acknowledge)
See the Microprocessor section of this datasheet for a description.
INT
B3
O
Interrupt Output
Active low signal. This signal is asserted "Low" when a change in alarm status
occurs. Once the status registers have been read, the interrupt pin will return
"High". GIE (Global Interrupt Enable) must be set "High" in the appropriate
global register to enable interrupt generation.
NOTE: This pin is an open-drain output that requires an external 10K
pull-up
resistor.
PCLK
AB2
I
Micro Processor Clock Input
In a synchronous microprocessor interface, PCLK is used as the internal tim-
ing reference for programming the LIU.
NOTE: Internally pulled "Low" with a 50k
resistor.
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