参数资料
型号: XRT83L38IB
厂商: Exar Corporation
文件页数: 57/87页
文件大小: 0K
描述: IC LIU T1/E1/J1 OCTAL 225BGA
标准包装: 84
类型: 线路接口装置(LIU)
驱动器/接收器数: 8/8
规程: T1,E1,J1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 225-BGA
供应商设备封装: 225-BGA(19x19)
包装: 托盘
XRT83L38
57
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.2
D7
Reserved
RO
0
D6
DMOIE_n
DMO Interrupt Enable: Writing a “1” to this bit enables DMO
interrupt generation, writing a “0” masks it.
R/W
0
D5
FLSIE_n
FIFO Limit Status Interrupt Enable: Writing a “1” to this bit
enables interrupt generation when the FIFO limit is within to 3
bits, writing a “0” to masks it.
R/W
0
D4
LCVIE_n
Line Code Violation Interrupt Enable: Writing a “1” to this bit
enables Line Code Violation interrupt generation, writing a “0”
masks it.
R/W
0
D3
NLCDIE_n
Network Loop-Code Detection Interrupt Enable: Writing a
“1” to this bit enables Network Loop-code detection interrupt
generation, writing a “0” masks it.
R/W
0
D2
AISDIE_n
AIS Interrupt Enable: Writing a “1” to this bit enables Alarm
Indication Signal detection interrupt generation, writing a “0”
masks it.
R/W
0
D1
RLOSIE_n
Receive Loss of Signal Interrupt Enable: Writing a “1” to this
bit enables Loss of Receive Signal interrupt generation, writing
a “0” masks it.
R/W
0
D0
QRPDIE_n
QRSS Pattern Detection Interrupt Enable: Writing a “1” to
this bit enables QRSS pattern detection interrupt generation,
writing a “0” masks it.
R/W
0
TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION
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