参数资料
型号: XA3S1600E-4FGG400Q
厂商: Xilinx Inc
文件页数: 25/37页
文件大小: 0K
描述: IC FPGA SPARTAN-3E 1600K 400FBGA
标准包装: 60
系列: Spartan®-3E XA
LAB/CLB数: 3688
逻辑元件/单元数: 33192
RAM 位总计: 663552
输入/输出数: 304
门数: 1600000
电源电压: 1.14 V ~ 1.26 V
安装类型: 表面贴装
工作温度: -40°C ~ 125°C
封装/外壳: 400-BGA
供应商设备封装: 400-FBGA(21x21)
DS635 (v2.0) September 9, 2009
Product Specification
31
R
Master Serial and Slave Serial Mode Timing
Table 38: Timing for the Master Serial and Slave Serial Configuration Modes
Symbol
Description
Slave/
Master
-4 Speed Grade
Units
Min
Max
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Both
1.5
10.0
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the active edge of
the CCLK pin
Both
11.0
-ns
Hold Times
TCCD
The time from the active edge of the CCLK pin to the point when
data is last held at the DIN pin
Both
0
-ns
Clock Timing
TCCH
High pulse width at the CCLK input pin
Master
Slave
TCCL
Low pulse width at the CCLK input pin
Master
Slave
FCCSER
Frequency of the clock signal at
the CCLK input pin
No bitstream compression
Slave
0
66(2)
MHz
With bitstream compression
0
20
MHz
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 6.
2.
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
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