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| 型号： | THS10064IDA |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 4-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32 |
| 封装： | GREEN, PLASTIC, TSSOP-32 |
| 文件页数： | 21/42页 |
| 文件大小： | 527K |
| 代理商： | THS10064IDA |
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THS10064
SLAS255B – DECEMBER 1999 – REVISED DECEMBER 2002
www.ti.com
28
DATA_AV TYPE
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of
control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines
the polarity of DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P
BIT 4
DATA_T
DATA_AV TYPE
0
Active low level
0
1
Active low pulse
1
0
Active high level
1
Active high pulse
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive dependent of the
DATA_T selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge
of READ). The trigger condition is checked again after TL reads. For single conversion mode, DATA_AV type should
be programmed to active level mode.
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous
conversion mode. The next DATA_AV pulse (when the trigger condition is satisfied) is sent out the earliest, when the
TL values, written into the FIFO before, were read out by the processor.
Read Timing (using R/W, CS0-controlled)
Figure 38 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input
R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0
is the last external signal of CS0, CS1, and R/W which becomes valid.
90%
10%
tw(CS)
tsu(R/W)
th(R/W)
ta
th
td(CSDAV)
CS0
CS1
R/W
RD
D(0–9)
DATA_AV
Figure 38. Read Timing Diagram Using R/W (CS0-controlled)
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