参数资料
| 型号： | NCP5314MNR2 |
| 厂商： | ON Semiconductor |
| 文件页数： | 22/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK CPU 2/3/4PH 32QFN |
| 产品变化通告： | Product Discontinuation 30/Jun/2004 |
| 标准包装： | 1 |
| 应用： | 控制器，CPU |
| 输入电压： | 9.5 V ~ 13.2 V |
| 输出数： | 4 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP5314MNR2OSCT |
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NCP5314
I RMS,CNTL is the RMS value of the trapezoidal current in
the control MOSFET:
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
IRMS,CNTL + D
(20)
maintain a specified junction temperature at the worst case
ambient operating temperature.
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
I Lo,MAX is the maximum output inductor current:
where:
q T t (TJ * TA) PD
(28)
ILo,MAX + IO,MAX f ) D ILo 2
I Lo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAX f * D ILo 2
(21)
(22)
θ T is the total thermal impedance ( θ JC + θ SA );
θ JC is the junction?to?case thermal impedance of the
MOSFET;
θ SA is the sink?to?ambient thermal impedance of the
D + VOUT VIN
I O,MAX is the maximum converter output current.
D is the duty cycle of the converter:
(23)
Δ I Lo is the peak?to?peak ripple current in the output
inductor of value L o :
heatsink assuming direct mounting of the MOSFET (no
thermal “pad” is used);
T J is the specified maximum allowed junction temperature;
T A is the worst case ambient operating temperature.
For TO?220 and TO?263 packages, standard FR?4
copper clad circuit boards will have approximate thermal
D ILo + (VIN * VOUT) @ D (Lo @ fSW)
(24)
resistances ( θ SA ) as shown below:
R DS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Q switch is the post gate threshold portion of the
gate?to?source charge plus the gate?to?drain charge. This
may be specified in the data sheet or approximated from the
gate?charge curve as shown in the Figure 26.
Pad Size (in 2 /mm 2 )
0.50/323
0.75/484
1.00/645
1.50/968
Single?Sided
1 oz Copper
60?65 ° C/W
55?60 ° C/W
50?55 ° C/W
45?50 ° C/W
Qswitch + Qgs2 ) Qgd
(25)
As with any power design, proper laboratory testing
I g is the output current from the gate driver IC.
V IN is the input voltage to the converter.
f sw is the switching frequency of the converter.
Q G is the MOSFET total gate charge to obtain R DS(on) ;
commonly specified in the data sheet.
V g is the gate drive voltage.
Q RR is the reverse recovery charge of the lower MOSFET.
Q oss is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
should be performed to insure the design will dissipate the
required power under worst case operating conditions.
Variables considered during testing should include
maximum ambient temperature, minimum airflow,
maximum input voltage, maximum loading and component
variations (i.e., worst case MOSFET R DS(on) ). Also, the
inductors and capacitors share the MOSFET’s heatsinks and
will add heat and raise the temperature of the circuit board
and MOSFET. For any new design, it is advisable to have as
much heatsink area as possible. All too often, new designs are
found to be too hot and require re?design to add heatsinking.
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
) (Vfdiode @ IO,MAX 2 @ t_nonoverlap @ fSW)
(26)
7. Adaptive Voltage Positioning
Two resistors program the Adaptive Voltage Positioning
(AVP): R FB and R DRP . These components form a resistor
where:
Vf diode is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non?overlap time between the upper
and lower gate drivers to prevent cross conduction.
This time is usually specified in the data sheet for the
control IC.
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non?overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
divider, shown in Figures 27 and 28, between V DRP , V FB ,
and V OUT .
Resistor R FB is connected between V OUT and the V FB pin
of the controller. At no load, this resistor will conduct the
very small internal bias current of the V FB pin. Therefore
V FB should be kept below 10 k Ω to avoid output voltage
error due to the input bias current. If the R FB resistor is kept
small, the V FB bias current can be ignored.
Resistor R DRP is connected between the V DRP and V FB
pins of the controller. At no load, these pins should be at an
equal potential, and no current should flow through R DRP . In
reality, the bias current coming out of the V DRP pin is likely
IRMS,SYNCH + 1 * D
(27)
to have a small positive voltage with respect to V FB . This
current produces a small decrease in output voltage at no
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2) 3]1 2
load, which can be minimized by keeping the R DRP resistor
http://onsemi.com
22
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