参数资料
型号: MPC8568ECVTAQGG
厂商: Freescale Semiconductor
文件页数: 115/139页
文件大小: 0K
描述: MPU POWERQUICC III 1023-PBGA
标准包装: 24
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 1023-BBGA,FCBGA
供应商设备封装: 1023-FCPBGA(33x33)
包装: 托盘
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
77
PCI Express
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
NOTE
The reference impedance for return loss measurements is 50. to ground for
both the D+ and D- line (that is, as measured by a Vector Network Analyzer
with 50. probes—see Figure 51). Note that the series capacitors, CTX, are
optional for the return loss measurement.
Figure 50. Minimum Receiver Eye Timing and Voltage Compliance Specification
14.5.1
Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within 0.2
inches of the package pins, into a test/measurement load shown in Figure 51.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary.
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