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参数资料
| 型号： | MC7457VG867NC |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 56/71页 |
| 文件大小： | 0K |
| 描述： | IC MPU RISC 867MHZ 483FCCBGA |
| 标准包装： | 36 |
| 系列： | MPC74xx |
| 处理器类型： | 32-位 MPC74xx PowerPC |
| 速度： | 867MHz |
| 电压： | 1.1V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 483-BCBGA，FCCBGA |
| 供应商设备封装： | 483-FCCBGA（29x29） |
| 包装： | 托盘 |
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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Features
Freescale Semiconductor
6
— Space must be available in the CQ for an instruction to dispatch (this includes instructions that
are assigned a space in the CQ but not in an issue queue)
Rename buffers
— 16 GPR rename buffers
— 16 FPR rename buffers
— 16 VR rename buffers
Dispatch unit
— Decode/dispatch stage fully decodes each instruction
Completion unit
— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all
instructions ahead of it have been completed, the instruction has finished execution, and no
exceptions are pending.
— Guarantees sequential programming model (precise exception model)
— Monitors all dispatched instructions and retires them in order
— Tracks unresolved branches and flushes instructions after a mispredicted branch
— Retires as many as three instructions per clock cycle
Separate on-chip L1 instruction and data caches (Harvard architecture)
— 32-Kbyte, eight-way set associative instruction and data caches
— Pseudo least recently used (PLRU) replacement algorithm
— 32-byte (eight-word) L1 cache block
— Physically indexed/physical tags
— Cache write-back or write-through operation programmable on a per-page or per-block basis
— Instruction cache can provide four instructions per clock cycle; data cache can provide four
words per clock cycle
— Caches can be disabled in software.
— Caches can be locked in software.
— MESI data cache coherency maintained in hardware
— Separate copy of data cache tags for efficient snooping
— L1 cache supports parity generation and checking
— No snooping of instruction cache except for icbi instruction
— Data cache supports AltiVec LRU and transient instructions
— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word
forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical
double-word forwarding.
Level 2 (L2) cache interface
— On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache
— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches
— A total nine-cycle load latency for an L1 data cache miss that hits in L2
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| MC74A5-33SNTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| MC74A5-50T | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| MC74AC00 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:QUAD 2-INPUT NAND GATE |
| MC74AC00D | 功能描述:逻辑门 2-6V Quad 2-Input RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
| MC74AC00DG | 功能描述:逻辑门 2-6V Quad 2-Input NAND RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
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