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参数资料
| 型号： | MAX6956ATL+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 3/24页 |
| 文件大小： | 0K |
| 描述： | IC DRVR DSPL LED 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 显示器类型： | LED |
| 接口： | I²C |
| 电流 - 电源： | 180µA |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
2-Wire-Interfaced, 2.5V to 5.5V, 20-Port or
28-Port LED Display Driver and I/O Expander
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2.5V to 5.5V, T A = T MIN to T MAX , unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V+ = 2.5V, V LED = 2.3V at maximum LED
current
9.5
13.5
18
Port Drive LED Sink Current,
Port Configured as LED Driver
I DIGIT
V+ = 3.3V, V LED = 2.4V at maximum LED
current (Note 2)
18.5
24
27.5
mA
V+ = 5.5V, V LED = 2.4V at maximum LED
current
19
25
30
Port Drive Logic Sink Current,
Port Configured as LED Driver
I DIGIT_SC
V+ = 2.5V, V OUT = 0.6V at maximum sink
current
V+ = 5.5V, V OUT = 0.6V at maximum sink
current
18.5
19
23
24
28
28
mA
Input High-Voltage SDA, SCL,
AD0, AD1
Input Low-Voltage SDA, SCL,
AD0, AD1
V IH
V IL
0.7 ?
V+
0.3 ?
V+
V
V
Input Leakage Current SDA, SCL
Input Capacitance
Output Low-Voltage SDA
I IH , I IL
V OL
(Note 2)
I SINK = 6mA
-50
50
10
0.4
nA
pF
V
TIMING CHARACTERISTICS (Figure 2)
(V+ = 2.5V to 5.5V, T A = T MIN to T MAX , unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
Bus Free Time Between a STOP
and a START Condition
Hold Time (Repeated) START
Condition
Repeated START Condition
Setup Time
STOP Condition Setup Time
f SCL
t BUF
t HD, STA
t SU, STA
t SU, STO
1.3
0.6
0.6
0.6
400
kHz
μs
μs
μs
μs
Data Hold Time
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Rise Time of Both SDA and SCL
Signals, Receiving
Fall Time of Both SDA and SCL
Signals, Receiving
Fall Time of SDA Transmitting
t HD, DAT
t SU, DAT
t LOW
t HIGH
t R
t F
t F , TX
(Note 3)
(Notes 2, 4)
(Notes 2, 4)
(Notes 2, 5)
15
100
1.3
0.7
20 +
0.1C b
20 +
0.1C b
20 +
0.1C b
900
300
300
250
ns
ns
μs
μs
ns
ns
ns
Pulse Width of Spike Suppressed t SP
(Notes 2, 6) 0 50 ns
Capacitive Load for Each Bus
Line
C b
(Note 2) 400 pF
Note 1: All parameters tested at T A = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to V IL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: C b = total capacitance of one bus line in pF. t R and t F measured between 0.3V+ and 0.7V+.
Note 5: I SINK ≤ 6mA. C b = total capacitance of one bus line in pF. t R and t F measured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
_______________________________________________________________________________________
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