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参数资料
| 型号： | MAX16063TG+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/13页 |
| 文件大小： | 0K |
| 描述： | IC PWR MNTR/OVRVOLT PROT 24TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 电源监控器，过压保护 |
| 电源电压： | 1 V ~ 5.5 V |
| 电流 - 电源： | 45µA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
1% Accurate, Low-Voltage,
Quad Window Voltage Detector
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.0V to 5.5V, T A = -40 ° C to +125 ° C, unless otherwise specified. Typical values are at V CC = 3.3V, T A = +25 ° C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V CC = 3.3V, I SINK = 10mA, RESET asserted
0.3
RESET Output-Voltage Low
V OL
V CC = 2.5V, I SINK = 6mA, RESET asserted
0.3
V
V CC = 1.2V, I SINK = 50μA, RESET asserted
0.3
RESET Output-Voltage High
MR Input-Voltage Low
MR Input-Voltage High
MR Minimum Pulse Width
MR Glitch Rejection
MR to RESET Delay
V OH
V IL
V IH
V CC ≥ 2.0V, I SOURCE = 6μA, RESET
deasserted
0.8 x
V CC
0.7 x
V CC
1
100
200
0.3 x
V CC
V
V
V
μs
ns
ns
MR Pullup Resistance
12
20
28
k ?
OUTPUTS ( UVOUT_ / OVOUT_ )
UVOUT_ , OVOUT_ Output-
Voltage Low
UVOUT_ , OVOUT_ Output-
Voltage High
UVIN_/OVIN_ to UVOUT_ /
OVOUT_ Propagation Delay
V OL
V OH
t D
V CC = 3.3V, I SINK = 2mA
V CC = 2.5V, I SINK = 1.2mA
V CC ≥ 2.0V, I SOURCE = 6μA
(V TH - 100mV) to (V TH + 100mV)
0.8 x
V CC
20
0.3
0.3
V
V
μs
DIGITAL LOGIC
MARGIN Input-Voltage Low
MARGIN Input-Voltage High
V IL
V IH
0.7 x
V CC
0.3 x
V CC
V
V
MARGIN Pullup Resistance
MARGIN Delay Time
t MD
Pulled up to V CC
Rising or falling (Note 5)
12
20
50
28
k ?
μs
Note 1:
Note 2:
Note 3:
Note 4:
Devices are tested at T A = +25 ° C and guaranteed by design for T A = T MIN to T MAX .
The outputs are guaranteed to remain asserted down to V CC = 1V.
Measured with MR and MARGIN unconnected.
The minimum and maximum specifications for this parameter are guaranteed by using the worse case of the SRT current
and SRT threshold specifications.
Note 5: Amount of time required for logic to lock/unlock outputs from margin testing.
_______________________________________________________________________________________
3
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